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參數(shù)資料
| 型號： | XRT82L38 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| 中文描述： | 八進制E1/T1/J1線收發(fā)器時鐘恢復(fù)和抖動衰減器（八的T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）） |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT82L38 |
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XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
21
be configured for Protected Monitoring purpose ac-
cording to ITU-G.772 standard.
With Protected Monitoring feature enabled as de-
tailed in Pin 59 description, the receiver input of chan-
nel 7 can be internally connected to any of the other
seven receiver input or transmitter output for both dig-
ital or bipolar signal monitoring. Digital signal is avail-
able at RxPOS7/RxNEG7 and RxClk7 and bipolar
signal is available at TTIP7/TRING7 when channel 7
is configured in Remote Loop-back Mode.
JTAG BOUNDARY SCAN
XRT82L38 supports IEEE 1149.1 boundary scan
standard for testing the integrity of the digital paths
between devices on a circuit board level. The JTAG
block consists of 4 signals and a set of JTAG registers
A simplified diagram of the implementation of IEEE
1149.1 is shown in Figure 11.
Test Clock (TCK)
is a Clock input to Syncronize
the test logic.
Test Mode Select (TMS)
is an input (with an inter-
nal pullup resistor) that is sampled on the rising
edge of TCK to sequence the TAP controller
’
s state
machine.
Test Data In (TDI)
is an input (with an internal pul-
lup resistor) that is sampled on the rising edge of
TCK.
Test Data Out (TDO)
is a tri-stateable data output
that is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge
of TCK.
F
IGURE
11. D
IAGRAM
OF
THE
I
MPLEMENTATION
OF
IEEE 1149.1
Boundary Register
Bypass
Decoder
3-Bit Instruction Register
M
U
X
M
U
X
TAP Controller
TDI
TCK
TMS
TDO
194
0
0
VDD
VDD
2
1
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