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參數(shù)資料
| 型號： | XRT73L03BIV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 38/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
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XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
41
3.5.2
The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applications
When the XRT73L03B is operating in the DS3 or
STS-1 Mode, then each channel declares and clears
LOS based upon the following two criteria.
Analog LOS (ALOS) Declaration/Clearance Crite-
ria
Digital LOS (DLOS) Declaration/Clearance Crite-
ria
In the DS3 Mode, the LOS output (RLOS) is simply
the logical "OR" of the ALOS and DLOS states.
1. The Analog LOS (ALOS) Declaration/Clearance
Criteria
A channel declares an Analog LOS (ALOS_(n)) Con-
dition if the amplitude of the incoming line signal
drops below a specific amplitude as defined by the
voltage at the LOSTHR input pin, and whether the
Receive Equalizer is enabled or not.
Table 5 presents the various voltage levels at the
LOSTHR input pin, the state of the Receive Equalizer
and the corresponding ALOS (Analog LOS) threshold
amplitudes.
Declaring ALOS
A channel(n) declares ALOS_(n) whenever the ampli-
tude of the receive line signal falls below the Signal
Level to Declare ALOS levels, as specified inTable 5.
Clearing ALOS_(n)
A channel(n) clears ALOS_(n) whenever the ampli-
tude of the receive line signal increases above the
Signal Level to Clear ALOS levels, as specified in
There is approximately a 2dB hysteresis in the re-
ceived signal level that exists between declaring and
clearing ALOS_(n) in order to prevent chattering in
the RLOS_(n) output signal.
Monitoring the State of ALOS_(n)
FIGURE 27. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RES-
TORATION OF
SIGNAL
Actual Occurrence
of LOS Condition
Line Signal
is Restored
Time Range for
LOS Declaration
Time Range for
LOS Clearance
G.775
Compliance
G.775
Compliance
0 UI
10 UI
0 UI
10 UI
255 UI
RTIP/
RRing
RLOS Output Pin
TABLE 5: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR &
REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION
REQEN SETTING
LOSTHR SETTING
SIGNAL LEVEL TO
DECLARE ALOS
SGNAL LEVEL TO CLEAR
ALOS
DS3
11
<22mV
>90mV
01
<17mV
>70mV
STS-1
11
<25mV
>115mV
01
<20mV
>90mV
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03BIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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