- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9995 > XRT73L03BIV (Exar Corporation)IC LIU E3/DS3/STS-1 3CH 120LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT73L03BIV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 33/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
37
When the System Manufacturer is interfacing the Re-
ceive Section of the XRT73L03B to the Cross-Con-
nect, they should be aware of the following facts:
1. All DS3 or STS-1 line signals that are present at
either the DSX-3 or the STSX-1 Cross Connect
are required to meet the Isolated Pulse Template
Requirements per Bellcore GR-499-CORE for
DS3 applications, or Bellcore GR-253-CORE for
STS-1 applications.
2. Bellcore documents state that the amplitude of
these pulses at the DSX-3 or STSX-1 location
can range in amplitude from 360mVpk to
850mVpk.
3. Bellcore documents stipulate that the Receiving
Terminal must be able to receive the pulse tem-
plate compliant line signal over a cable length of
0 to 450 feet from the DSX-3 or the STSX-1
Cross-Connect location.
These facts are reflected in Figure 23.
Design Considerations for DS3 and STS-1 Appli-
cations
When installing equipment into environments depict-
ed in Figure 23, the system installation personnel
may be able to determine the cable length between
the local terminal equipment and the DSX-3/STSX-1
Cross-Connect Patch-Panel. The cable length be-
tween the local terminal equipment and the DSX-3/
STSX-1 Cross-Connect Patch Panel ranges between
0 and 450 feet.
It is extremely unlikely that the system installation
personnel will know the cable length between the
DSX-3/STSX-1 Cross-Connect Patch-Panel and the
remote terminal equipment. Therefore, we recom-
mend that the Receive Equalizer be enabled by set-
ting the REQEN_(n) input pin or bit-field to “1”.
The only time that the Receive Equalizer should be
disabled is when there is an off-chip equalizer in the
Receive path between the DSX-3/STSX-1 Cross-
Connect and the RTIP_(n)/RRING_(n) input pins, or
in applications where the Receiver is directly monitor-
ing the transmit output signal directly.
3.2.1.2
Design Considerations for E3 Applica-
tions
In E3 System installation, it is recommended that the
Receive Equalizer of the XRT73L03B device be en-
abled by pulling the REQEN_(n) input pins “High” or
by setting the REQEN_(n) bit-fields to “1”.
NOTE: The results of extensive testing indicates that when
the Receive Equalizer is enabled, the XRT73L03B device is
capable of receiving an E3 line signal with anywhere from 0
to 12dB of cable loss over the Industrial Temperature
range.
Design Considerations for E3 Applications or if
the Overall Cable Length is known
If during System Installation the overall cable length is
known, then in order to optimize the performance of
the XRT73L03B in terms of receive intrinsic jitter, etc.,
enable or disable the Receive Equalizer based upon
the following recommendations:
The Receive Equalizer should be turned ON if the
Receive Section of a given channel is going to re-
ceive a line signal with an overall cable length of 300
feet or greater. Conversely, turn OFF the Receive
Equalizer if the Receive Section of a given channel is
going to receive a line signal over a cable length of
less than 300 feet.
NOTES:
1. If the Receive Equalizer block is turned ON when it
is receiving a line signal over short cable length, the
received line signal may be over-equalized which
could degrade performance by increasing the
amount of jitter that exists in the recovered data
and clock signals or by creating bit-errors
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the trans-
mitting terminal to the receiving terminal. However,
the Receive Equalizer was not designed to counter
flat loss where all of the Fourier frequency compo-
nents within the line signal are subject to the same
amount of attenuation. Flat loss is handled by the
AGC block.
Disable the Receive Equalizer block by doing either of
the following.
a. Operating in the Hardware Mode
Set the REQEN_(n) input pin “Low".
b. Operating in the HOST Mode
Write a "0" to the REQEN_(n) bit-field within Com-
mand Register CR2, as illustrated below.
COMMAND REGISTER CR2-(n)
D4
D3
D2
D1
D0
Reserved
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
XX
X
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72825LB15PF | IC FIFO SYNC DL 1024X18 128TQFP |
| MS27472T12F35P | CONN RCPT 22POS WALL MNT W/PINS |
| IDT72V3650L6PFG8 | IC FIFO SS 2048X36 6NS 128-TQFP |
| MS3100A28-2P | CONN RCPT 14POS WALL MNT W/PINS |
| MS27473E10F35SA | CONN PLUG 13POS STRAIGHT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03BIV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。