參數(shù)資料
型號： XE8807AMI026TLF
廠商： Semtech
文件頁數(shù)： 86/143頁
文件大?。?/td> 0K
描述： IC MCU LOW PWR MTP FLASH 32-TQFP
標(biāo)準(zhǔn)包裝： 1
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（11 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
包裝： 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： XE8807AMI026DKR
Semtech 2006
www.semtech.com
7-8
XE8806A/XE8807A
The oscillator characteristics are given in Table 7-11. The characteristics are valid only if the crystal and board
layout meet the specifications above.
Symbol
Description
Min
Typ
Max
Unit
Comments
fXtal
Nominal frequency
32768
Hz
St_xtal
Start-up time
1
2
s
Fstab
Frequency deviation
-100
300
ppm
Note 1
Table 7-11. Crystal oscillator characteristics.
Note 1. This gives the relative frequency deviation from nominal for a crystal with CL=8.2pF and within the
temperature range -40
°C to 85°C. The crystal tolerance, crystal aging and crystal temperature drift are not
included in this figure.
7.8
External clock
7.8.1
External clock configuration
The user can provide an external clock instead of the internal oscillators. The external provided frequency is
internally divided by two. The external clock input pin is XIN.
The system is configured for external clock by bit EnExtClock in register RegSysClock. Using the bits in the
registers RegSysRcTrim1 and RegSysRcTrim2, the ck32kHz clock frequency can be controlled (see section
7.11).
Note: when using the external clock, the Xtal is not available.
7.8.2
External clock specification
The external clock has to satisfy the specifications in the table below. Correct behavior of the circuit can not be
guaranteed if the external clock signal does not respect the specifications below.
Symbol
Description
Min
Typ
Max
Unit
Comments
FEXT
External clock
frequency
8
MHz
Note 1
PW_1
Pulse 1 width
0.06
s
Note 1
PW_0
Pulse 0 width
0.03
20
s
Note 1
FEXT_LV
External clock
frequency
TBD
kHz
Note 2
PW_1_LV
Pulse 1 width
TBD
s
Note 2
PW_0_LV
Pulse 0 width
TBD
20
s
Note 2
Table 7-12. External clock specifications.
Note 1. For VBAT
≥2.4V
Note 2. For VBAT=VREG=1.2V
7.9
Clock source selection
There are three possible clock sources available for the CPU clock. The RC clock is always selected after power-
up, a negative pulse on NRESET or after Sleep mode. The CPU clock selection is done with the bit CpuSel in
RegSysClock (0= fastest clock, 1= 32 kHz from Xtal if EnableXtal =1 and EnExtClock = 0 else from high
prescaler 32 kHz output).
Switching from one clock source to another is glitch free.
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