參數(shù)資料
型號: XE8807AMI026TLF
廠商: Semtech
文件頁數(shù): 74/143頁
文件大?。?/td> 0K
描述: IC MCU LOW PWR MTP FLASH 32-TQFP
標準包裝: 1
系列: XE880x
應用: 感測機
核心處理器: Coolrisc816?
程序存儲器類型: 閃存(11 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數(shù): 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
包裝: 標準包裝
供應商設(shè)備封裝: 32-TQFP(7x7)
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱: XE8807AMI026DKR
Semtech 2006
www.semtech.com
6-3
XE8806A/XE8807A
Pos.
RegSysCtrl
Rw
Reset
Function
7
SleepEn
r w
0 nresetcold
enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
6
EnResetPConf
r w
0 nresetcold
enables the nresetpconf signal when the
nresetglobal is active
0: nresetpconf is disabled
1: nresetpconf is enabled
5
EnBusError
r w
0 nresetcold
enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
4
EnResetWD
r w
0 nresetcold
enables reset from Watchdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
3 – 0
-
r
0000
unused
Table 6-2. RegSysCtrl register.
Pos.
RegSysReset
Rw
Reset
Function
7
Sleep
rw
0 nresetglobal
Sleep mode control (reads always 0)
6
SleepFlag
r c
0 nresetcold
Sleep mode was active before
5
ResetBusError
r c
0 nresetcold
reset source was BusError
4
ResetWD
r c
0 nresetcold
reset source was Watchdog
3
ResetfromportA
r c
0 nresetcold
reset source was Port A combination
2 – 0
r
000
unused
Table 6-3. RegSysReset register
Pos.
RegSysWd
Rw
Reset
Function
7 - 4
-
r
0000
unused
WDKey[3]
w
Watchdog Key bit 3
3
WDCounter[3]
r
0 nresetglobal
Watchdog counter bit 3
WDKey[2]
w
Watchdog Key bit 2
2
WDCounter[2]
r
0 nresetglobal
Watchdog counter bit 2
WDKey[1]
w
Watchdog Key bit 1
1
WDCounter[1]
r
0 nresetglobal
Watchdog counter bit 1
WDKey[0]
w
Watchdog Key bit 0
0
WDCounter[0]
r
0 nresetglobal
Watchdog counter bit 0
Table 6-4. RegSysWd register
6.4
Reset handling capabilities
There are 5 reset sources:
Power On Reset (POR)
External reset from the NRESET pin
Programmable port A input combination
Programmable watchdog timer reset
Programmable BusError reset on processor access outside the allocated memory map
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