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參數(shù)資料
| 型號： | XE8807AMI026TLF |
| 廠商： | Semtech |
| 文件頁數(shù)： | 109/143頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU LOW PWR MTP FLASH 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XE880x |
| 應(yīng)用： | 感測機 |
| 核心處理器： | Coolrisc816? |
| 程序存儲器類型： | 閃存（11 kB） |
| 控制器系列： | XE8000 |
| RAM 容量： | 512 x 8 |
| 接口： | UART，USRT |
| 輸入/輸出數(shù)： | 24 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
| 配用： | XE8000MP-ND - PROG BOARD AND PROSTART2 CARD |
| 其它名稱： | XE8807AMI026DKR |
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Semtech 2006
www.semtech.com
11-5
XE8806A/XE8807A
The snap-to-rail function connects a pullup or pulldown resistor to the input pin depending on the value forced on
the input pin. This function can be used for instance when the input port is connected to a tristate bus. When the
bus is floating, the pullup or pulldown maintains the bus in the last low impedance state before it became floating
until another low impedance output drives the bus. It also reduces the power consumption with respect to a classic
pullup since it selects the pullup or pulldown resistor so that it confirms the detected input state.
The state of input pin is summarized in the table below.
PAPullup[x]
PASnaptorail[x]
(last) externally
forced PA[x]
value
PA[x] pull
0
x
floating
1
0
x
pullup
1
0
pulldown
1
pullup
Table 11-11: Snap-to-rail
Port A starts up with the pullup resistor connected and the snap-to-rail function disabled.
Port A as an interrupt source:
Each Port A input is an interrupt request source and can be set on rising or falling edge with the corresponding bit
in RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can
be debounced by setting register RegPADebounce. The interrupt signals are sampled on the fastest clock in the
circuit. In order to guarantee that the circuit detects the interrupt, the minimal pulse length should be 1 cycle of this
clock.
Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The
change of this register may result in a transition, which may be interpreted as a valid interruption.
Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
Port A as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM peripheral.
Port A as a reset source:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0]
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-12.
PARes1[x]
PARes0[x]
PAReset[x]
0
1
PA[x]
1
0
not(PA[x])
1
Table 11-12: Selection bits for reset signal
A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting
both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresponding pin. Setting
both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a
reset by software.
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