參數(shù)資料
型號： XE8807AMI026TLF
廠商： Semtech
文件頁數(shù)： 55/143頁
文件大小： 0K
描述： IC MCU LOW PWR MTP FLASH 32-TQFP
標(biāo)準(zhǔn)包裝： 1
系列： XE880x
應(yīng)用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（11 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
包裝： 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： XE8807AMI026DKR
Semtech 2006
www.semtech.com
3-3
XE8806A/XE8807A
Register name
Register function
r0
general purpose
r1
general purpose
r2
general purpose
r3
data memory offset
i0h
MSB of the data memory index i0
i0l
LBS of the data memory index i0
i1h
MSB of the data memory index i1
i1l
LBS of the data memory index i1
i2h
MSB of the data memory index i2
i2l
LBS of the data memory index i2
i3h
MSB of the data memory index i3
i3l
LBS of the data memory index i3
iph
MSB of the program memory index ip
ipl
LBS of the program memory index ip
stat
status register
a
accumulator
Table 3-1. CPU internal register definition
bit
name
function
7
IE2
enables (when 1) the interrupt request of level 2
6
IE1
enables (when 1) the interrupt request of level 1
5
GIE
enables (when 1) all interrupt request levels
4
IN2
interrupt request of level 2. The interrupts labelled “l(fā)ow” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
3
IN1
interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
2
IN0
interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
1
EV1
event request of level 1. The events labelled “l(fā)ow” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
0
EV0
event request of level 1. The events labelled “hig” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
Table 3-2. Status register description
The CPU also has a number of flags that can be used for conditional jumps. These flags are defined in Table 3-3.
symbol
name
function
Z
zero
Z=1 when the accumulator a content is zero
C
carry
This flag is used in shift or arithmetic operations.
For a shift operation, it has the value of the bit that was shifted out (LSB for shift
right, MSB for shift left).
For an arithmetic operation with unsigned numbers:
it is 1 at occurrence of an overflow during an addition (or equivalent).
it is 0 at occurrence of an underflow during a subtraction (or equivalent).
V
overflow
This flag is used in shift or arithmetic operations.
For arithmetic or shift operations with signed numbers, it is 1 if an overflow or
underflow occurs.
Table 3-3. Flag description
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