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參數(shù)資料
| 型號： | XE8807AMI026TLF |
| 廠商： | Semtech |
| 文件頁數(shù)： | 130/143頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU LOW PWR MTP FLASH 32-TQFP |
| 標準包裝： | 1 |
| 系列： | XE880x |
| 應用： | 感測機 |
| 核心處理器： | Coolrisc816? |
| 程序存儲器類型： | 閃存（11 kB） |
| 控制器系列： | XE8000 |
| RAM 容量： | 512 x 8 |
| 接口： | UART，USRT |
| 輸入/輸出數(shù)： | 24 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 包裝： | 標準包裝 |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
| 配用： | XE8000MP-ND - PROG BOARD AND PROSTART2 CARD |
| 其它名稱： | XE8807AMI026DKR |
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Semtech 2006
www.semtech.com
14-7
XE8806A/XE8807A
14.8.1
Input data filter and bit synchronization
14.8.1.1
NRZ code
When the NRZ codes are used, the bit synchronization clock should be extracted from the preamble since the
coding itself may not contain clock information. The input data filter has to be used (see description below in
section 14.8.1.2) to extract the bit synchronization clock. The bit RfifRxClock in register RegRfifCmd2 is to be
cleared to 0. If the input data stream contains long periods without transitions, the internally generated bit
synchronization clock could slip with respect to the bit rate resulting in transmission errors (see also specification in
chapter 14.11). Tests have shown a very robust behavior with the internal bit synchronizer though.
An external bit synchronization clock can be used. This clock has to be delivered on the pin RFIF1. The bit stream
on RFIF0 is then sampled on detection of the rising edge of the clock on the RFIF1 pin. This function has to be
enabled by setting bit RfifRxClock in register RegRfifCmd2 to 1. Selecting this function bypasses the input filter.
In practice, it was found that the synchronization was more reliable with the internal synchronization filter than with
the external bit clock.
14.8.1.2
Bi-phase and Miller code
The bi-phase and Miller code include clock information and no external bit synchronization clock is needed. The
input data filter is used to filter the noise on the input data. The filter samples the input data at 16 times the selected
baud rate and performs the following majority function on 8 successive samples:
if (number of ’1’ in the last 8 samples >= 6)
data = 1
if (number of ‘1’ in the last 8 samples <= 2)
data = 0
else data = former data
The filter has some hysteresis since the output does not change when the number of 1’s is between 2 and 6.
The input filter is always selected for the bi-phase and Miller coding independent from the value of the bit
RfifRxClock in register RegRfifCmd2.
14.8.2
Start Sequence Detection or message synchronization
A full message is mainly composed of three parts:
1) a preamble or start sequence
2) the data itself
3) an optional stop sequence.
A start sequence is necessary to indicate the start of a new message.
The interface supports the detection of several types of start sequences. The user can chose between these start
sequence detection modes using the bits RfifEnStart[1:0] in RegRfifCmd2 as shown in Table 14-13. The actual
implementation of the detection mode differs depending on the selected PCM coding and is described below.
A start sequence detection will set the bit RfifRxStartDet in the register RegRfifRxSta and generate an interrupt
on the Irq_Rfif_Rx line. The contents of the reception FIFO is reset. The data of the preceding message that were
not yet read at the occurrence of a new start sequence are lost. The first bit in the FIFO is the first valid bit decoded
after the detected start sequence.
The bit RfifRxStartDet has to be cleared by software by writing a 1 to the bit.
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