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參數(shù)資料
| 型號(hào)： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 8/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
16
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Multiple Register Write Timing
The minimum timing requirements for sequential write
cycles are shown in Figure 12. Sequential write cycles are
identical to single write cycles except that the chip enable
(MPCE) and output enable (MPOE) signals do not need to
be de-asserted between write cycles.
Data Buffer Ready Timing
The data buffer ready (MPBRDY) signal indicates whether
the data buffer is ready to accept new data during a write
cycle or whether the data buffer contains valid data to be
read during a read cycle. The data buffer itself is sixteen
words deep, where each word is 16 bits wide.
The data buffer mode transfer direction is identified by the
state of the DATABUFMODE bit in the STATUSREG regis-
ter:
DATABUFMODE = 0 indicates data buffer read mode
DATABUFMODE = 1 indicates data buffer write mode
The data buffer mode depends on the type of command that
was issued to the System ACE CF controller. If an Identi-
fyMemCard or ReadMemCard command was issued, then
the data buffer remains in read mode until the command is
finished executing (i.e., all sector data has been read from
the buffer). If a WriteMemCard command was issued, then
the data buffer remains in write mode until the command is
finished executing (i.e., all sector data has been written to
the buffer).
Figure 12: Multiple WORD Writes to ACE Register(s)
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
22
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
ADDRESS <0>
ADDRESS <1>
DATA <0>
DATA <1>
tSA
tSCE
tH
tSWE
tH
tSD
tSOE
tSA
tH
tSD
tH
tSWE
tH
DS080_17_020101
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