參數(shù)資料
型號(hào)： XCCACE-TQG144I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 62/69頁(yè)
文件大?。?/td> 0K
描述： IC ACE CONTROLLER CHIP TQ144
產(chǎn)品變化通告： XCCACE-TQG144I Discontinuation 31/Oct/2011
標(biāo)準(zhǔn)包裝： 60
控制器類型： ACE 控制器
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 30mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 管件
其它名稱： 122-1511-5
System ACE CompactFlash Solution
DS080 (v3.0) April 7, 2014
65
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
CFREG
3OUT2
VCCH
N/A
CompactFlash register select line (active LOW);
this pin is always driven to a 1 but is provided here
for future compatibility.
CFWE
131
OUT2
VCCH
N/A
CompactFlash write enable line (active LOW)
CFOE
123
OUT2
VCCH
N/A
CompactFlash output enable line (active LOW)
CFWAIT
140
IN
VCCH
N/A
CompactFlash memory cycle wait flag (active
LOW)
CFRSVD
133
IN
VCCH
Ext. Pull-up
This pin must be pulled up to VCCH using an
external pull-up resistor.
CFCD1
103
IN
VCCH
Int. Pull-up
CompactFlash card detect line 1 (active LOW)
CFCD2
13
IN
VCCH
Int. Pull-up
CompactFlash card detect line 2 (active LOW)
CFGADDR0
86
IN
VCCL
Int. Pull-down
Configuration address select pin 0
CFGADDR1
87
IN
VCCL
Int. Pull-down
Configuration address select pin 1
CFGADDR2
88
IN
VCCL
Int. Pull-down
Configuration address select pin 2
CFGMODEPIN
89
IN
VCCL
Int. Pull-up
Configuration mode pin:
When 0, this pin instructs the System ACE CF
controller to start the configuration process
when the CFGSTART bit is set in the
CONTROLREG register in the MPU interface.
When 1, this pin instructs the System ACE CF
controller to start the configuration process
immediately following reset.
TSTTDI
102
IN
VCCH
Int. Pull-up
Test JTAG port test data input
TSTTCK
101
IN
VCCH
N/A
Test JTAG port test clock
TSTTMS
98
IN
VCCH
Int. Pull-up
Test JTAG port test mode select
TSTTDO
97
OUT3
VCCH
Ext. Pull-up(1)
Test JTAG port test data output
CFGTDO
82
OUT3
VCCL
Ext. Pull-up(1)
Configuration JTAG test data output
CFGTDI
81
IN
VCCL
Int. Pull-up
Configuration JTAG test data input
CFGTCK
80
OUT2
VCCL
N/A
Configuration JTAG test clock
CFGTMS
85
OUT3
VCCL
Ext. Pull-up(1)
Configuration JTAG test mode select
CFGINIT
78
IN
VCCL
Int. Pull-up
Configuration JTAG INIT pin (active LOW); this pin
is used to sense when all devices are ready to be
programmed (i.e., INIT = 1 indicates target
device(s) are ready to receive configuration data
and INIT = 0 indicates that the target device(s) are
being cleared and are not ready to be configured)
POR_BYPASS
108
IN
VCCH
Int. Pull-down
Power-on-reset (POR) bypass input; used in
conjunction with POR_RESET to bypass the
internal POR circuit in favor of using an external
board-level POR circuit; the internal POR circuit is
bypassed when POR_BYPASS = 1; the
POR_BYPASS pin should be held at a static 0 or 1
while the System ACE CF controller is receiving
power.
Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output)
Pin Name
Pin #
I/O Type
I/O Supply Rail
Termination
Description
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