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參數(shù)資料
| 型號(hào)： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 46/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
50
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Write Data Buffer Control Flow Process
The control flow process for writing to the data buffer is
shown in Figure 29, page 49. The System ACE data buffer
is implemented as a 32-byte (16-word) deep FIFO that is
aliased across a range of MPU byte addresses (40h
through 7Fh) in order to facilitate burst transfers across the
MPU interface. Sector data is written to the data buffer by
first waiting for the buffer to become ready (i.e., empty of
any sector data), as shown in Figure 26, page 46. Once the
buffer is ready, then all 32 bytes can be written to the buffer
to alternating even and odd byte addresses. Writing to an
odd byte address while in BYTE mode causes the FIFO to
increment the data word to the next available word in the
FIFO. Writing to any data buffer address while in WORD
mode will cause the FIFO to increment.
Microprocessor (MPU) to Configuration JTAG (CFGJTAG) Setup
This setup provides an MPU to CFGJTAG communication path. The data configures the FPGA system through JTAG via the
Configuration JTAG Port.
The System ACE CF controller handles all necessary steps to perform configuration using the MPU communication path to
the target system. Figure 31, page 51 shows the connections required for this setup.
Figure 30: Data Flow Diagram of MPU to CFGJTAG
TSTTDI
TAP
CTRL.
TSTTDO
TDO
TDI
CFGTDO
CFGTDI
TDI
TDO
TDI
TDO
TDI
DS080_30_030801
*CFCGTCK and CFGTMS lines are driven
by ACE Controller Core Logic and are broadcast
to all target devices.
BS
N
A
C
MPU
CompactFlash
ACE
Controller
Core
(Test JTAG Port)
(Configuration JTAG Port)
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