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| 型號： | XCCACE-TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 48/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ACE CONTROLLER CHIP TQ144 |
| 產(chǎn)品變化通告： | XCCACE-TQG144I Discontinuation 31/Oct/2011 |
| 標準包裝： | 60 |
| 控制器類型： | ACE 控制器 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 30mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 管件 |
| 其它名稱： | 122-1511-5 |
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System ACE CompactFlash Solution
52
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Write Data to CFGJTAG Interface Control Flow
Process
The target devices in the CFGJTAG chain can also be pro-
grammed via the MPU interface as shown in Figure 32,
page 53. The following steps should be taken to write con-
figuration data to the CFGJTAG controller:
1.
Arbitrate for the data buffer by requesting a
CompactFlash lock as shown in Figure 23, page 43.
Once the lock has been granted, go to step 2.
2.
Put the CFGJTAG controller into the reset state by
setting CFGRESET=1 (bit 7 of the CONTROLREG
register, MPU byte address 18h).
3.
Direct the CFGJTAG controller to wait for CFGSTART=1
to begin configuration by setting FORCECFGMODE=1
(bit 3 of the CONTROLREG register, MPU byte address
18h) and CFGMODE=0 (bit 4 of the CONTROLREG
register, MPU byte address 18h).
4.
Directs the CFGJTAG controller to start receiving ACE
configuration information from the MPU port when
CFGRESET is released by setting CFGSTART=1 (bit 5
of the CONTROLREG register, MPU byte address 18h)
and CFGSEL=1 (bit 6 of the CONTROLREG register,
MPU byte address 18h).
5.
Release the CFGJTAG controller from the Reset state
and cause it to wait for ACE configuration data from the
MPU port by setting CFGRESET=0 (bit 7 of the
CONTROLREG register, MPU byte address 18h).
6.
Initialize the Buffer Count variable.
7.
Perform the Write Data Buffer process. All ACE file
information should be sent with the exception of the first
512 bytes of the file. Note that an entire buffer’s worth of
data should be written to the buffer to ensure that it gets
sent to the CFGJTAG controller.
Notes:
Note: The first 512 bytes of the ACE file comprise a comment
header and do not contain valid ACE instructions and
therefore should not be written to the CFGJTAG controller via
the MPU port. The configuration engine does this
automatically when processing the ACE file from CF, but it
does not do this for ACE information coming from the MPU
port.Failure to strip off the first 512 bytes will result in
CFGFAILED=1 and CFGINSTRERR=1 in the ERRORREG
register.
8.
Decrement the Buffer Count variable.
9.
Check configuration status. If a configuration error
exists, stop writing data to the MPU port and return the
error condition. If no error, go to step 10.
10. Check the Buffer Count variable. If Buffer Count is not 0,
go back to step 7. If Buffer Count is 0, then go to
11. Check to see if the configuration process has
completed successfully by checking for CFGDONE=1
(bit 7 of the STATUSREG register, MPU byte address
04h). If this is not the case, then other bits of the
STATUSREG and ERRORREG register should indicate
the status of the configuration process. If CFGDONE=1,
then go to step 12.
12. Set CFGRESET=1 (bit 7 of the CONTROLREG
register, MPU byte address 18h) and CFGSTART=0 (bit
5 of the CONTROLREG register, MPU byte address
18h). This puts the configuration engine into the Reset
state and directs it not to start again if CFGRESET is
subsequently released.
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