參數(shù)資料
型號(hào)： XCCACE-TQG144I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 4/69頁(yè)
文件大?。?/td> 0K
描述： IC ACE CONTROLLER CHIP TQ144
產(chǎn)品變化通告： XCCACE-TQG144I Discontinuation 31/Oct/2011
標(biāo)準(zhǔn)包裝： 60
控制器類型： ACE 控制器
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 30mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 管件
其它名稱： 122-1511-5
System ACE CompactFlash Solution
12
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
MPU Timing Description
This section contains timing diagrams for the MPU interface. Parameters used in the timing diagrams are described in
Single Register Read Cycle
The single register read cycle is shown in Figure 9,
page 13. A single register read is accomplished by assert-
ing a valid address (MPA), asserting the chip enable (MPCE
= LOW) and de-asserting the write enable (MPWE = HIGH)
during the first clock cycle (Cycle 0). These signals should
hold these values at least until the rising edge of the fourth
clock cycle (Cycle 3).
The output enable signal should be asserted (MPOE =
LOW) during the third clock cycle (Cycle 2). Register data
associated with the specified address appears on the MPD
bus two clock cycles after the falling edge of MPCE during
the assertion of MPCE. The register read cycle is then com-
pleted by de-asserting the output enable during the fourth
clock cycle (Cycle 3).
MPWE
1In
LOW
Synchronous active LOW write enable. A high-to-low-to-high transition must
occur on MPWE in three consecutive clock cycles in order for the write to take
place.During a valid write cycle, MPCE must be LOW and MPD must be valid
during the clock cycle that MPWE.
MPOE
1In
LOW
Asynchronous active LOW output enable. Both MPOE and MPCE must be
LOW to read from the MPU interface. When either MPOE or MPCE is HIGH,
the MPD pins of the System ACE CF controller are in a high-impedance state.
MPBRDY
1
Out
HIGH
Synchronous active HIGH buffer ready output. During data buffer read mode
MPBRDY is HIGH when the data in the DATABUF buffer is valid. During data
buffer write mode MPBRDY is HIGH when data can be written to the
DATABUF buffer.
MPIRQ
1
Out
HIGH
Synchronous active HIGH interrupt request output. MPIRQ HIGH indicates
that an interrupt condition has occurred in the MPU interface. All interrupt
conditions must be manually cleared before MPIRQ will go LOW. MPIRQ is
always LOW when interrupts are disabled.
Table 6: MPU Interface Port Signal Description (Continued)
Name
Width
Direction
Active
Description
Table 7: MPU Interface Timing Parameters
Symbol
Parameter
Min
Max
Units
tSA
Address setup time
4
--
ns
tSCE
Chip enable setup time
4
--
ns
tSWE
Write enable setup time
12
--
ns
tSOE
Output enable setup time
12
--
ns
tSD
Data setup time
4
--
ns
tDD
Clock HIGH to valid data
--
22
ns
tDOE
Chip/Output enable LOW to valid data
--
13
ns
tDBRDY
Clock HIGH to buffer ready valid
--
22
ns
tH
Hold time
4
--
ns
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