
7
User’s Manual U14046EJ3V0UD
Major Revisions in This Edition (1/3)
Page
Description
Throughout
Addition of the following products
PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A),
PD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A),
PD78F0034B, 78F0034B(A), 78F0034BY, 78F0034BY(A)
Addition of the following packages
64-pin plastic LQFP (GC-8BS type)
73-pin plastic FBGA (F1-CN3 type)
Addition of expanded-specification products to
PD780024A, 780034A Subseries
p.34
Addition of 1.1 Expanded-Specification Products and Conventional Products
p.54
Addition of 1.10 Correspondence Between Mask ROM Versions and Flash Memory Versions
p.54
Modification of 1.11 Differences Between Standard Grade Products and Special Grade Products
p.55
Addition of 1.12 Correspondence Between Products and Packages
p.74
Addition of 2.9 Correspondence Between Mask ROM Versions and Flash Memory Versions
p.75
Modification of 2.10 Differences Between Standard Grade Products and Special Grade Products
p.75
Addition of 2.11 Correspondence Between Products and Packages
p.84
Addition of description of pin processing in 3.2.18 VPP (flash memory versions only)
p.85
Modification of Table 3-1 Pin I/O Circuit Types
p.96
Addition of description of pin processing in 4.2.18 VPP (flash memory versions only)
p.97
Modification of Table 4-1 Pin I/O Circuit Types
p.108
Addition of description of program area in 5.1.2 Internal data memory space
pp.116, 117
Modification of Figure 5-14 Data to Be Saved to Stack Memory and Figure 5-15 Data to Be Restored from
Stack Memory
p.130
Modification of [Description example] in 5.4.4 Short direct addressing
pp.133 to 135
Addition of [Illustration] in 5.4.7 Based addressing, 5.4.8 Based indexed addressing, and 5.4.9 Stack
addressing
pp.140 to 160
Modification of port block diagram (Figures 6-2 Block Diagram of P00 to P03 to 6-23 Block Diagram of P74
and P75)
p.163
Addition of Table 6-6 Port Mode Registers and Output Latch Settings When Alternate Function Is Used
pp.171, 174
Addition of description of internal feedback resistor and oscillation stabilization time select register (OSTS) in
7.3 Clock Generator Control Registers
p.185
Modification of Figure 8-1 Block Diagram of 16-Bit Timer/Event Counter 0
pp.186, 187
Modification of Tables 8-2 TI00/TO0/P70 Pin Valid Edge and CR00, CR01 Capture Trigger and 8-3 TI01/
P71 Pin Valid Edge and CR00 Capture Trigger in 2nd edition to Table 8-2 CR00 Capture Trigger and Valid
Edges of TI00 and TI01 Pins and Table 8-3 CR01 Capture Trigger and Valid Edge of TI00 Pin (CRC02
= 1)
p.194
Modification of description procedure of each function in 8.4 Operation of 16-Bit Timer/Event Counter 0
p.208
Addition of Figure 8-26 PPG Output Configuration Diagram and Figure 8-27 PPG Output Operation Timing
p.209
Addition of 8.5 Program List
pp.216, 218
Modification of 8.6 (3) Capture register data retention timing and addition of (11) STOP mode or main
system clock stop mode setting