
26
User’s Manual U14046EJ3V0UD
LIST OF FIGURES (4/8)
Figure No.
Title
Page
12-1
Block Diagram of Clock Output/Buzzer Output Controller ...................................................................
252
12-2
Format of Clock Output Select Register (CKS) ...................................................................................
254
12-3
Format of Port Mode Register 7 (PM7) ................................................................................................
255
12-4
Remote Control Output Application Example ......................................................................................
256
13-1
8-Bit A/D Converter Block Diagram .....................................................................................................
258
13-2
Format of A/D Converter Mode Register 0 (ADM0) .............................................................................
262
13-3
Format of Analog Input Channel Specification Register 0 (ADS0) ......................................................
263
13-4
Basic Operation of 8-Bit A/D Converter ...............................................................................................
265
13-5
Relationship Between Analog Input Voltage and A/D Conversion Result ............................................
267
13-6
A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................
269
13-7
A/D Conversion by Software Start .......................................................................................................
270
13-8
Overall Error .........................................................................................................................................
271
13-9
Quantization Error ................................................................................................................................
271
13-10
Zero Scale Error ...................................................................................................................................
272
13-11
Full Scale Error ....................................................................................................................................
272
13-12
Integral Linearity Error .........................................................................................................................
272
13-13
Differential Linearity Error ....................................................................................................................
272
13-14
Circuit Configuration of Series Resistor String ....................................................................................
274
13-15
A/D Conversion End Interrupt Request Generation Timing .................................................................
275
13-16
Timing of Reading Conversion Result (When Conversion Result Is Undefined) .................................
276
13-17
AVDD Pin Connection ...........................................................................................................................
276
13-18
Example of Connecting Capacitor to AVREF Pin ...................................................................................
277
13-19
Internal Equivalent Circuit of Pins ANI0 to ANI7 ..................................................................................
277
13-20
Example of Connection If Signal Source Impedance Is High ..............................................................
278
14-1
10-Bit A/D Converter Block Diagram ...................................................................................................
280
14-2
Format of A/D Conversion Result Register 0 (ADCR0) .......................................................................
281
14-3
Format of A/D Converter Mode Register 0 (ADM0) .............................................................................
284
14-4
Format of Analog Input Channel Specification Register 0 (ADS0) ......................................................
285
14-5
Basic Operation of 10-Bit A/D Converter .............................................................................................
287
14-6
Relationship Between Analog Input Voltage and A/D Conversion Result ............................................
289
14-7
A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................
290
14-8
A/D Conversion by Software Start .......................................................................................................
291
14-9
Overall Error .........................................................................................................................................
292
14-10
Quantization Error ................................................................................................................................
292
14-11
Zero Scale Error ...................................................................................................................................
293
14-12
Full Scale Error ....................................................................................................................................
293
14-13
Integral Linearity Error .........................................................................................................................
293
14-14
Differential Linearity Error ....................................................................................................................
293