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SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
16.4.2 Slow Clock Generator
The SUPC embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is
supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC
oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 s).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
The command is made by writing the SUPC Control Register (SUPC_CR) with the XTALSEL bit at 1.This results in a
sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then
enables the crystal oscillator, then counts a number of slow RC oscillator clock periods to cover the start-up time of the
crystal oscillator (refer to electrical characteristics for details of 32KHz crystal oscillator start-up time), then switches the
slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The switching time
may vary according to the slow RC oscillator clock frequency range. The switch of the slow clock source is glitch free.
The OSCSEL bit of the SUPC Status Register (SUPC_SR) allows knowing when the switch sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to
provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical
characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the SUPC Mode Register (SUPC_MR)
needs to be set at 1.
16.4.3 Supply Monitor
The SUPC embeds a supply monitor which is located in the VDDIO Power Supply and which monitors VDDIO power
supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power supply
drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.62V to 2V by steps of 100 mV. This
threshold is programmed in the SMTH field of the SUPC Supply Monitor Mode Register (SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock
periods, according to the choice of the user. This can be configured by programming the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption
respectively by factors of 2, 16 and 128, if the user does not need a continuous monitoring of the VDDIO power supply.
A supply monitor detection can either generate a reset of the core power supply or a wake-up of the core power supply.
Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in
SUPC_SMMR.
The SUPC provides two status bits in the SUPC_SR for the supply monitor:
The SMOS bit provides real time information, which is updated at each measurement cycle or updated at each
slow clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of
SUPC_SR.
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in SUPC_SMMR.