
592
SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
27.7.5.6
High-Speed Slave Mode
High-speed mode is enabled when the HSEN bit is written to one in TWIHS_CR. Furthermore, the analog pad filter must
be enabled, the PADFEN bit must be written to one in TWIHS_FILTR and the FILT bit must be cleared. TWI High-speed
mode operation is similar to TWI operation with the following exceptions:
1.
A master code is received first at normal speed before entering high-speed mode period.
2.
When TWI high-speed mode is active, clock stretching is only allowed after acknowledge (ACK), not-acknowledge
(NACK), START (S) or repeated START (Sr) (as consequence OVF may happen).
TWI high-speed mode allows transfers of up to 3.4 Mbit/s.
The TWI slave in high-speed mode requires that slave clock stretching is disabled (SCLWSDIS bit at ‘1’). The peripheral
clock must run at a minimum of 11 MHz.
Note:
When slave clock stretching is disabled, the TWIHS_RHR must always be read before receiving the next data
(MASTER write frame). It is strongly recommended to use either the polling method on the RXRDY flag in
TWIHS_SR, or the PDC. If the receive is managed by an interrupt, the TWI interrupt priority must be set to the
right level and its latency minimized to avoid receive overrun.
Note:
When slave clock stretching is disabled, the TWIHS_THR must be filled with the first data to send before the
beginning of the frame (MASTER read frame). It is strongly recommended to use either the polling method on
the TXRDY flag in TWIHS_SR, or the PDC. If the transmit is managed by an interrupt, the TWI interrupt priority
must be set to the right level and its latency minimized to avoid transmit underrun.
Read/Write Operation
A TWI high-speed frame always begins with the following sequence:
1.
START condition (S)
2.
Master Code (0000 1XXX)
3.
Not-acknowledge (NACK)
When the TWI is programmed in slave mode and TWI high-speed mode is activated, master code matching is activated
and internal timings are set to match the TWI high-speed mode requirements.
Figure 27-43. High-Speed Mode Read/Write
Usage
27.7.5.7
Slave Read Write Flowcharts
The flowchart shown in
Figure 27-44 gives an example of read and write operations in Slave mode. A polling or interrupt
method can be used to check the status bits. The interrupt method requires that the Interrupt Enable Register
(TWIHS_IER) be configured first.
NA
SADR
R/W
S
MASTER CODE
DATA
A/NA
P
Sr
A
NA
SADR
R/W
S
MASTER CODE
DATA
A/NA
Sr
A
SADR
P
F/S Mode
HS Mode
F/S Mode