參數(shù)資料
型號： UPD70F3025AGC-33-8EU-A
廠商： Renesas Electronics America
文件頁數(shù)： 42/49頁
文件大?。?/td> 0K
描述： MCU 32BIT 256K FLASH 100LQFP
標準包裝： 50
系列： V853
核心處理器： V850ES
芯體尺寸： 32-位
速度： 33MHz
連通性： CSI，EBI/EMI，UART/USART
外圍設(shè)備： PWM
輸入/輸出數(shù)： 67
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b，D/A 2x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
2011 Microchip Technology Inc.
DS31037B-page 47
PIC24F16KL402 FAMILY
5.0
FLASH PROGRAM MEMORY
The PIC24F16KL402 family of devices contains
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable when operating with VDD over
1.8V.
Flash memory can be programmed in three ways:
In-Circuit Serial Programming (ICSP)
Run-Time Self Programming (RTSP)
Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24F device to be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for the programming clock
and programming data (which are named PGECx and
PGEDx, respectively), and three other lines for power
(VDD), ground (VSS) and Master Clear/Program mode
E
ntry Voltage (MCLR/VPP). This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
Run-Time Self Programming (RTSP) is accomplished
using TBLRD (table read) and TBLWT (table write)
instructions. With RTSP, the user may write program
memory data in blocks of 32 instructions (96 bytes) at
a time, and erase program memory in blocks of 32, 64
and 128 instructions (96,192 and 384 bytes) at a time.
The NVMOP<1:0> (NVMCON<1:0>) bits decide the
erase block size.
5.1
Table Instructions and Flash
Programming
Regardless of the method used, Flash memory
programming is done with the table read and write
instructions. These allow direct read and write access to
the program memory space from the data memory while
the device is in normal operating mode. The 24-bit target
address in the program memory is formed using the
TBLPAG<7:0> bits and the Effective Address (EA) from
a W register, specified in the table instruction, as
depicted in Figure 5-1.
The TBLRDL and TBLWTL instructions are used to read
or write to bits<15:0> of program memory. TBLRDL and
TBLWTL
can access program memory in both Word
and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Flash Pro-
gramming, refer to the “PIC24F Family
Reference Manual”
, Section 4. “Program
Memory”
(DS39715).
0
Program Counter
24 Bits
Program
TBLPAG Reg
8 Bits
Working Reg EA
16 Bits
Using
Byte
24-Bit EA
0
1/0
Select
Table
Instruction
Counter
Using
User/Configuration
Space Select
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