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參數(shù)資料
| 型號： | UPD70F3025AGC-33-8EU-A |
| 廠商： | Renesas Electronics America |
| 文件頁數(shù)： | 21/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 256K FLASH 100LQFP |
| 標準包裝： | 50 |
| 系列： | V853 |
| 核心處理器： | V850ES |
| 芯體尺寸： | 32-位 |
| 速度： | 33MHz |
| 連通性： | CSI，EBI/EMI，UART/USART |
| 外圍設備： | PWM |
| 輸入/輸出數(shù)： | 67 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b，D/A 2x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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PIC24F16KL402 FAMILY
DS31037B-page 28
2011 Microchip Technology Inc.
3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
R/W-0
—
—DC
bit 15
bit 8
R/W-0(1)
R/W-0(1)
R/W-0(1)
R-0
R/W-0
IPL2(2)
IPL1(2)
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented:
Read as ‘0’
bit 8
DC:
ALU Half Carry/Borrow bit
1
= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0
= No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL<2:0>:
CPU Interrupt Priority Level (IPL) Status bits(1,2)
111
= CPU Interrupt Priority Level is 7 (15); user interrupts disabled
110
= CPU Interrupt Priority Level is 6 (14)
101
= CPU Interrupt Priority Level is 5 (13)
100
= CPU Interrupt Priority Level is 4 (12)
011
= CPU Interrupt Priority Level is 3 (11)
010
= CPU Interrupt Priority Level is 2 (10)
001
= CPU Interrupt Priority Level is 1 (9)
000
= CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT
Loop Active bit
1
= REPEAT loop in progress
0
= REPEAT loop not in progress
bit 3
N:
ALU Negative bit
1
= Result was negative
0
= Result was non-negative (zero or positive)
bit 2
OV:
ALU Overflow bit
1
= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0
= No overflow has occurred
bit 1
Z:
ALU Zero bit
1
= An operation, which effects the Z bit, has set it at some time in the past
0
= The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
bit 0
C:
ALU Carry/Borrow bit
1
= A carry-out from the Most Significant bit (MSb) of the result occurred
0
= No carry-out from the Most Significant bit (MSb) of the result occurred
Note 1:
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2:
The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
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