參數(shù)資料
型號(hào)： UPD70F3025AGC-33-8EU-A
廠商： Renesas Electronics America
文件頁數(shù)： 26/49頁
文件大小： 0K
描述： MCU 32BIT 256K FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 50
系列： V853
核心處理器： V850ES
芯體尺寸： 32-位
速度： 33MHz
連通性： CSI，EBI/EMI，UART/USART
外圍設(shè)備： PWM
輸入/輸出數(shù)： 67
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b，D/A 2x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
2011 Microchip Technology Inc.
DS31037B-page 32
PIC24F16KL402 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address, as
shown in Figure 4-2.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard-coded program
execution vectors. A hardware Reset vector is provided
to redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
PIC24F devices also have two Interrupt Vector Tables
(IVT), located from 000004h to 0000FFh and 000104h
to 0001FFh. These vector tables allow each of the
many device interrupt sources to be handled by
separate ISRs. A more detailed discussion of the
Interrupt Vector Tables is provided in Section 8.1
.
4.1.3
DATA EEPROM
In the PIC24F16KL402 family, the data EEPROM is
mapped to the top of the user program memory space,
starting at address, 7FFE00, and expanding up to
address, 7FFFFF.
The data EEPROM is organized as 16-bit wide memory
and 256 words deep. This memory is accessed using
table read and write operations, similar to the user code
memory.
4.1.4
DEVICE CONFIGURATION WORDS
Table 4-1 provides the addresses of the device
Configuration Words for the PIC24F16KL402 family.
Their location in the memory map is shown in
For more information on device Configuration Words,
TABLE 4-1:
DEVICE CONFIGURATION
WORDS FOR PIC24F16KL402
FAMILY DEVICES
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
Configuration Words
Configuration Word
Addresses
FBS
F80000
FGS
F80004
FOSCSEL
F80006
FOSC
F80008
FWDT
F8000A
FPOR
F8000C
FICD
F8000E
0
8
16
PC Address
000000h
000002h
000004h
000006h
23
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
least significant word
most significant word
Instruction Width
000001h
000003h
000005h
000007h
msw
Address
(lsw Address)
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