參數(shù)資料
型號： UPD70F3025AGC-33-8EU-A
廠商： Renesas Electronics America
文件頁數(shù)： 24/49頁
文件大小： 0K
描述： MCU 32BIT 256K FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 50
系列： V853
核心處理器： V850ES
芯體尺寸： 32-位
速度： 33MHz
連通性： CSI，EBI/EMI，UART/USART
外圍設(shè)備： PWM
輸入/輸出數(shù)： 67
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b，D/A 2x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
PIC24F16KL402 FAMILY
DS31037B-page 30
2011 Microchip Technology Inc.
3.3.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
32-bit signed/16-bit signed divide
2.
32-bit unsigned/16-bit unsigned divide
3.
16-bit signed/16-bit signed divide
4.
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.3.3
MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided in Table 3-2.
TABLE 3-2:
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Instruction
Description
ASR
Arithmetic shift right source register by one or more bits.
SL
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
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