參數(shù)資料
型號(hào)： UPD70F3025AGC-33-8EU-A
廠商： Renesas Electronics America
文件頁(yè)數(shù)： 22/49頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT 256K FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 50
系列： V853
核心處理器： V850ES
芯體尺寸： 32-位
速度： 33MHz
連通性： CSI，EBI/EMI，UART/USART
外圍設(shè)備： PWM
輸入/輸出數(shù)： 67
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b，D/A 2x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
2011 Microchip Technology Inc.
DS31037B-page 29
PIC24F16KL402 FAMILY
3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
division for a 16-bit divisor.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several Multiplication modes:
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
REGISTER 3-2:
CORCON: CPU CONTROL REGISTER
U-0
—
bit 15
bit 8
U-0
R/C-0
R/W-0
U-0
—
—IPL3(1)
PSV
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented:
Read as ‘0’
bit 3
IPL3:
CPU Interrupt Priority Level Status bit(1)
1
= CPU Interrupt Priority Level is greater than 7
0
= CPU Interrupt Priority Level is 7 or less
bit 2
PSV:
Program Space Visibility in Data Space Enable bit
1
= Program space is visible in data space
0
= Program space is not visible in data space
bit 1-0
Unimplemented:
Read as ‘0’
Note 1:
User interrupts are disabled when IPL3 = 1.
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