參數(shù)資料
型號： UPD70F3025AGC-33-8EU-A
廠商： Renesas Electronics America
文件頁數(shù)： 35/49頁
文件大?。?/td> 0K
描述： MCU 32BIT 256K FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 50
系列： V853
核心處理器： V850ES
芯體尺寸： 32-位
速度： 33MHz
連通性： CSI，EBI/EMI，UART/USART
外圍設(shè)備： PWM
輸入/輸出數(shù)： 67
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b，D/A 2x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
2011
Micr
ochip
T
e
ch
nol
ogy
I
n
c.
DS
31037B
-page
40
PIC24
F16KL
402
FAMILY
TABLE 4-10:
PORTA REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7(1)
Bit 6
Bit 5(2)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
—
TRISA7
TRISA6
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
00DF
PORTA
02C2
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
—
—LATA7
LATA6
—
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA
02C6
—
—ODA7
ODA6
—
ODA4
ODA3
ODA2
ODA1
ODA0
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
These ports and their associated bits are unimplemented on 14-pin and 20-pin devices; read as ‘0’.
2:
PORTA<5> is unavailable when MCLR functionality is enabled (MCLRE Configuration bit = 1).
TABLE 4-11:
PORTB REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13(1)
Bit 12(1)
Bit 11(2)
Bit 10(2)
Bit 9
Bit 8
Bit 7(1)
Bit 6(2)
Bit 5(2)
Bit 4
Bit 3(2)
Bit 2(1)
Bit 1(1)
Bit 0
All
Resets
TRISB
02C8
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02CA
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
ODCB
02CE
ODB15
ODB14
ODB13
ODB12
ODB11
ODB10
ODB9
ODB8
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
These ports and their associated bits are unimplemented on 14-pin and 20-pin devices.
2:
These ports and their associated bits are unimplemented in 14-pin devices.
TABLE 4-12:
PAD CONFIGURATION REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PADCFG1 02FC
—
SDO2DIS(1) SCK2DIS(1) SDO1DIS SCK1DIS
—
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’.
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