參數(shù)資料
型號： TMS418169P-80
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 9/67頁
文件大?。?/td> 1464K
代理商： TMS418169P-80
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
Table 3. Pin Description Versus Operational Mode
PIN
DRAM
TRANSFER
SAM
A0
–
A8
Row, column address
Row address, tap point
RAS
Row-address strobe
Row-address strobe
CASL
CASU
Column-address strobe, DQ output enable
Tap-address strobe
DSF
Block-write enable
Load-write-mask-register enable
Load-color-register enable
CBR (option reset)
Split-register-transfer enable
TRG
DQ output enable
Transfer enable
WE
Write enable, write-per-bit enable
DQx
DRAM data I/O, write mask
SC
Serial clock
SE
SQ output enable,
QSF output enable
SQx
Serial-data output
QSF
VCC
VSS
NC/GND
Serial-register status
Power supply
Ground
Make no external connection or tie to system GND
For proper device operation, all VCC pins must be connected to a 5.0-V supply and all VSS pins must be tied to ground.
pin definitions
address (A0
–
A8)
Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are
set up on pins A0
–
A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set
up on pins A0
–
A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on
or before the falling edge of RAS and the first falling edge of CASx.
In 4-column block-write operations (TMS5516x), column-address bits A0
–
A1 are ignored. Column-address bits
A2
–
A8 become the block address that selects one of the 128 blocks in the active row. In 8-column block write
operations (TMS5517x), column-address bits A0
–
A2 are ignored. Column address bits A3
–
A8 become the
block address that selects one of the 64 blocks in the active row.
In full-register operations, column-address bit A8 selects which half of the active row in the DRAM is transferred
to the SAM. Column address bits A0
–
A7 select one of 256 tap points (starting positions) for the serial-data
output.
In split-register-transfer operations, column address bit A8 selects the DRAM half row. Column-address bit A7
is ignored. The internal serial-address counter identifies which half of the SAM is in use. If the high half of the
SAM is in use, the low half of the SAM is loaded with the low half of the DRAM half row, and vice versa.
Column-address bits A0
–
A6 select one of 127 tap points (starting locations) for the serial output. Locations 127
and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are
not valid tap points in split-register-transfer operations.
row-address strobe (RAS)
The falling edge of RAS latches the states of the row address, CASL, CASU, DSF, TRG, WE, and the DQs onto
the chip to initiate DRAM and transfer functions. RAS also functions as a DRAM output enable.
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