參數(shù)資料
型號： TMS418169P-80
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 65/67頁
文件大?。?/td> 1464K
代理商： TMS418169P-80
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH 1996
65
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PARAMETER MEASUREMENT INFORMATION
RAS
CASx
ADDR
TRG
DSF
CASE I
SC
QSF
SC
QSF
SC
QSF
CASE II
CASE III
Tap1
(low)
Bit
127
Tap1
(high)
Bit
255
Tap2
(low)
Bit
127
Tap1
(low)
Row
Tap1
(high)
Row
Tap2
(low)
Row
Tap2
(high)
Row
Tap1
(low)
Tap2
(low)
Bit
127
Bit
255
Bit
127
Tap1
(low)
Tap2
(low)
Bit
127
Bit
255
Bit
127
Tap1
(high)
Tap1
(high)
Full-Register-Transfer Read
Split Register to the
High Half of the
Data Register
Split Register to the
Low Half of the
Data Register
Split Register to the
High Half of the
Data Register
NOTES: A. In order to achieve proper split-register operation, a full-register-transfer read should be performed before the first
split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then
begin either after the full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after
the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read
cycle and the first split-register cycle.
B. A split-register-transfer nto the nactive half s not allowed until td(MSRL) s met. td(MSRL) s the minimum delay time between the rising
edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the inactive
half. After the td(MSRL) is met, the split-register-transfer into the inactive half must also satisfy the minimum td(RHMS) requirement.
td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive half and the
rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 56. Split-Register Operating Sequence
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