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參數資料
| 型號： | TMS418169P-80 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數據輸出高速DRAM等 |
| 文件頁數： | 10/67頁 |
| 文件大小： | 1464K |
| 代理商： | TMS418169P-80 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
column-address strobe (CASL, CASU)
The first falling edge of CASx latches the states of the column address and DSF onto the chip to control DRAM
and transfer functions. CASL and CASU provide byte control in DRAM operations. CASL controls the lower byte
(DQ0
–
DQ7), and CASU controls the upper byte (DQ8
–
DQ15). Byte control can be applied in read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. CASx also functions
as a DRAM output enable.
special-function select (DSF)
DSF is latched on the falling edge of RAS and the falling edge of CASx to determine which functions are invoked
on a particular cycle (see Table 2).
output enable, transfer select (TRG)
TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS
selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG
also functions as DRAM output enable.
write enable, write-per-bit select (WE)
WE selects either the write mode or the read mode in a CASx cycle. Dropping WE low selects the write mode.
Holding WE high selects the read mode. Holding WE low on the falling edge of RAS selects the write-per-bit
operation.
DRAM data I/O, write mask, column mask (DQ0
–
DQ15)
DQ0
–
DQ15 function as the DRAM input/output port in DRAM operations. In normal DRAM write cycles, all
16 bits of write data are latched on either the falling edge of WE or the first falling edge of CASx, whichever
occurs later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in
load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the
DQs are latched as the write mask on the falling edge of RAS.
Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup
resistor required) with a fan-out of one Series 74 TTL load. The outputs are in the high-impedance (floating) state
until RAS, CASx, and TRG have all been brought low in read cycles. For the TMS551x0 devices, the outputs
remain valid until CASx is brought high, TRG is brought high, or WE is brought low. For the TMS551x1 devices,
the outputs remain valid until both RAS and CASx are brought high, TRG is brought high, or WE is brought low.
serial clock (SC)
The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM
location.
serial enable (SE)
SE functions as the output enable for SQ0
–
SQ15 and QSF. SE low enables the serial-data output. SE high
disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC
automatically increments the internal serial-address counter regardless of the state of SE.
serial data outputs (SQ0
–
SQ15)
SQ0
–
SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no
pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising
edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled.
special-function output (QSF)
QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal
serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal
serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance
state when SE is high.
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