參數(shù)資料
型號(hào)： TMS418169P-80
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁(yè)數(shù)： 12/67頁(yè)
文件大?。?/td> 1464K
代理商： TMS418169P-80
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
refresh
CAS-before-RAS (CBR) refresh
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external
row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles
are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode.
The CBRN (no reset) and CBRS (no reset and stop point set) refreshes do not end the persistent write-per-bit
mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively
as long as the entire refresh is completed within the required time period, t
rf(MA)
. The output buffers remain in
the high-impedance state during the CBR type refresh cycles regardless of the state of TRG.
hidden refresh
A hidden refresh is accomplished by holding either or both CASL and CASU low in the DRAM read cycle and
cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the
CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the
output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be
supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row
to be refreshed.
enhanced page mode (TMS551x0)
Enhanced page mode allows faster memory access by keeping the same row address while selecting random
column addresses. The maximum RAS low time and minimum CASx page cycle time are used to determine
the number of columns that can be accessed.
Unlike conventional page mode, the enhanced page mode allows the TMS551x0 to operate at a higher data
bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx goes low. A
valid column address can be presented immediately after the row-address hold time has been satisfied, usually
well in advance of the falling edge of CASx. In this case, data is obtained after t
a(C)
max (access time from CASx
low) if t
a(CA)
max (access time from column address) has been satisfied.
extended data output (TMS551x1)
The TMS551x1 features extended data output during DRAM accesses. While RAS and TRG are low, the DRAM
output remains valid even when CASx returns high. The output remains valid until WE is low, TRG is high, or
both CASx and RAS are high (see Figure 1, Figure 2, and Figure 3). The extended data-output mode functions
in all read cycles including DRAM read, page-mode read, and read-modify-write cycles.
Valid Output
tdis(RH)
RAS
CASx
DQ0
–
DQ15
TRG
See
“
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
”
table.
Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x1)
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