參數(shù)資料
型號： TMS418169P-80
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 21/67頁
文件大小： 1464K
代理商： TMS418169P-80
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
4-column block write (continued)
Every four adjacent columns makes a block, which results in 128 blocks along one row. Block 0 comprises
columns 0
–
3, block 1 comprises columns 4
–
7, block 2 comprises columns 8
–
11, etc., as shown in Figure 11.
0
1
2
3
4
5
6
7
511
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Columns
Block 0
Block 1
Block 127
. . . . . . . . . . . . . . . . . . . . . .
One Row of 0
–
511
Figure 11. 4-Column-Block Column-Organization
During 4-column block-write cycles, only the seven most significant column addresses (A2
–
A8) are latched on
the falling edge of CASx to decode one of the 128 blocks. Address bits A0
–
A1 are ignored. All one-megabit
quadrants have the same block selected.
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the falling
edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section
for details on the use of the write-mask capability, allowing additional performance options.
Example of block write:
block-write column address
= 110000000 (A0
–
A8 from left to right)
bit 0
= 1011
= 1110
= 1111
bit 15
color-data register
write-mask register
column-mask register
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
0111
1011
1010
4th
Quad
1st
Quad
Column-address bits A0 and A1 are ignored. Block 0 (columns 0
–
3) is selected for all one-megabit quadrants.
The first quadrant has DQ0
–
DQ2 written with bits 0
–
2 from the color-data register to all four columns of
block 0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0.
The second quadrant (DQ4
–
DQ7) has all four columns masked off due to the column-mask bits 4
–
7 being 0,
so that no data is written.
The third quadrant (DQ8
–
DQ11) has its four DQs written with bits 8
–
11 from the color-data register to columns
1
–
3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to the
column-mask bit 8 being 0.
The fourth quadrant (DQ12
–
DQ15) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous
data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 12 after
the 4-column block-write operation shown in the example.
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