參數(shù)資料
型號(hào)： TMS418169P-80
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 17/67頁
文件大?。?/td> 1464K
代理商： TMS418169P-80
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
write-per-bit
The write-per-bit function allows the masking of any combination of the 16 DQs on any write cycle. The
write-per-bit operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling
edge of RAS, the write operation is performed without any masking. There are two write-per-bit modes: the
nonpersistent write-per-bit and the persistent write-per-bit.
nonpersistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit
mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask
selects which of the 16 DQs are to be written and which are not. After RAS has latched the on-chip write-per-bit
mask, input data is driven onto the DQ pins and is latched on either the falling edge of WE or the first falling edge
of CASx, whichever occurs later. CASL enables the lower byte (DQ0
–
DQ7) to be written through the mask and
CASU enables the upper byte (DQ8
–
DQ15) to be written through the mask. If a write-mask-low (write
mask = 0) is strobed into a particular DQ pin on the falling edge of RAS, data is not written to that DQ. If a
write-mask-high (write mask = 1) is strobed into a particular DQ pin on the falling edge of RAS, data is written
to that DQ (see Figure 7).
RAS
CASL
CASU
WE
DQ0
–
DQ15
Valid Input
th(WLD)
tsu(DQR)
tsu(DWL)
th(RDQ)
Write Mask
See
“
timing requirements over recommended ranges of supply voltage and operating free-air temperature
”
table.
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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