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| 型號： | TMS418169P-80 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 38/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-80 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’
551xx-60
MIN
’
551xx-70
MIN
UNIT
SYMBOL
MAX
MAX
th(CLW)
th(RA)
th(RDQ)
th(RHrd)
th(RLCA)
th(RLD)
th(RLW)
th(RSF)
th(RWM)
th(SFC)
th(SFR)
th(SHSQ)
th(TRG)
th(WLD)
th(WLG)
td(CACH)
Hold time, WE low after first CASx low, early write
tWCH
tRAH
tMH
tRRH
tAR
tDHR
tWCR
tFHR
tRWH
tCFH
tRFH
tSOH
tTHH
tDH
tOEH
tCAL
10
15
ns
Hold time, row address after RAS low
10
10
ns
Hold time, write mask valid after RAS low, non-persistent write-per-bit
10
10
ns
Hold time, WE high after RAS high, read (see Note 12)
0
0
ns
Hold time, column address valid after RAS low (see Note 13)
30
30
ns
Hold time, data valid after RAS low (see Note 13)
35
35
ns
Hold time, WE low after RAS low, write
30
35
ns
Hold time, DSF after RAS low
30
35
ns
Hold time, WE low after RAS low, write-per-bit
10
10
ns
Hold time, DSF after first CASx low
10
10
ns
Hold time, DSF after RAS low
10
10
ns
Hold time, SQ after SC high
4
5
ns
Hold time, TRG after RAS low
10
10
ns
Hold time, data valid after WE low, late write
15
15
ns
Hold time, TRG high after WE low (see Note 14)
10
10
ns
Delay time, column address valid to CASx high
30
45
ns
td(CAGH)
Delay time, column address to TRG high in real-time-load and late-load
full-register transfer
tATH
20
20
ns
td(CARH)
Delay time, column address valid to RAS high
tRAL
30
35
ns
td(CASH)
Delay time, column address to first SC high after TRG high, early-load
full-register transfer
tASD
25
25
ns
td(CAWL)
td(CHRL)
td(CLGH)
Delay time, column address valid to WE low, read-modify-write
tAWD
tCRP
50
60
ns
Delay time, both CASx high to RAS low
0
0
ns
Delay time, CASx low to TRG high, read
17
20
ns
td(CLQSF)
Delay time, first CASx low to QSF switching, full-register transfer
(see Note 15)
tCQD
30
30
ns
td(CLRH)
td(CLRL)
Delay time, CASx low to RAS high
tRSH
tCSR
17
20
ns
Delay time, first CASx low to RAS low, CBR refresh
0
0
ns
td(CLSH)
Delay time, first CASx low to first SC high after TRG high, early-load
full-register transfer
tCSD
20
20
ns
td(CLTH)
Delay time, first CASx low to TRG high, real-time-load and late-load
full-register transfer
tCTH
15
15
ns
td(CLWL)
td(CLZ)
td(DCL)
td(DGL)
td(GHD)
Timing measurements are referenced to VIL max and VIH min.
NOTES: 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
15. TRG must disable the output buffers prior to applying data to the DQ pins.
16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is
VOH / VOL = 2 V/0.8 V.
Delay time, CASx low to WE low, read-modify-write (see Note 16)
tCWD
tCLZ
tDZC
tDZO
tOED
37
45
ns
Delay time, first CASx low to DQ in the low-impedance state
3
2
ns
Delay time, data to CASx low
0
0
ns
Delay time, data to TRG low
0
0
ns
Delay time, TRG high before data applied at DQ
10
15
ns
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