參數(shù)資料
型號(hào): TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號(hào)控制器(DSC)
文件頁數(shù): 44/166頁
文件大?。?/td> 1889K
代理商: TMS320F28335_1
www.ti.com
A
3.2.13 Oscillator and PLL
3.2.14 Watchdog
3.2.15 Peripheral Clocking
3.2.16 Low-Power Modes
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts
can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from GPIO32
– GPIO63 pins.
The F2833x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator
circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed
on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is
desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass
mode.
The F2833x devices contain a watchdog timer. The user software must regularly reset the watchdog
counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The
watchdog can be disabled if necessary.
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
The F2833x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
Turns off the internal oscillator. This mode basically shuts down the device and places it in
the lowest possible power consumption mode. A reset or external signal can wake the
device from this mode.
STANDBY:
HALT:
The F2833x device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PIE:
Flash:
XINTF:
DMA
Timers:
CSM:
ADC:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
External Interface Registers
DMA Registers
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
Functional Overview
44
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