參數(shù)資料
型號: TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號控制器(DSC)
文件頁數(shù): 142/166頁
文件大小: 1889K
代理商: TMS320F28335_1
www.ti.com
A
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 6-43. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) (continued)
MIN
MAX
UNIT
ns
ns
ns
t
a(XRD)
t
su(XD)XRD
t
h(XD)XRD
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR - 14
(1)
14
0
Table 6-44. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN
15
12
MAX
UNIT
ns
ns
ns
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
3
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
15
0
ns
ns
(1)
The first XREADY (synchronous) sample occurs with respect to E in
Figure 6-25
:
E = (XRDLEAD + XRDACTIVE) t
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each t
until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n – 1) t
– t
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-45. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
11
MAX
UNIT
ns
ns
ns
t
su(XRDYAsynchL)XCOHL
t
h(XRDYAsynchL)
t
e(XRDYAsynchH)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
8
3
t
su(XRDYAsynchH)XCOHL
t
h(XRDYasynchH)XZCSH
11
0
ns
ns
Electrical Specifications
142
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