參數(shù)資料
型號(hào)： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號(hào)控制器（DSC）
文件頁數(shù)： 141/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
Lead
Active
Trail
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
en(XD)XWEL
t
h(XD)XWEH
t
dis(XD)XRNW
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0 XZCS6 XZCS7
,
,
XRD
XWE0 XWE1
,
(D)
XR/W
XD[0:31], XD[0:15]
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
DOUT
XREADY
(E)
t
d(XWEL-XD)
XA[0:19]
(A) (B)
(C)
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
A.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
During alignment cycles, all signals transition to their inactive state.
XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles.
XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
For USEREADY = 0, the external XREADY input signal is ignored.
B.
C.
D.
E.
Figure 6-24. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
N/A
(1)
XRDACTIVE
N/A
(1)
XRDTRAIL
N/A
(1)
USEREADY
X2TIMING
XWRLEAD
≥
1
XWRACTIVE
≥
0
XWRTRAIL
≥
0
READYMODE
N/A
(1)
0
0
(1)
6.10.7.7
N/A = Not applicable (or “Don’t care”) for this example
External Interface Ready-on-Read Timing With One External Wait State
Table 6-42. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive
high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
MIN
MAX
UNIT
ns
ns
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
1
3
- 2
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XRDH)
t
h(XA)XZCSH
t
h(XA)XRD
2
1
1
ns
ns
ns
ns
ns
- 2
(1)
(1)
(1)
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-43. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ns
t
a(A)
Access time, read data from address valid
(LR + AR) - 16
(1)
(1)
LR = Lead period, read access. AR = Active period, read access. See
Table 6-37
.
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Electrical Specifications
141
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