參數(shù)資料
型號(hào): TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號(hào)控制器(DSC)
文件頁數(shù): 39/166頁
文件大小: 1889K
代理商: TMS320F28335_1
www.ti.com
A
3.2
Brief Descriptions
3.2.1
C28x CPU
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 3-5. Wait-states
Area
Wait-States (CPU)
0-wait
0-wait (writes)
1-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
Wait-States (DMA)
(1)
Comments
Fixed
M0 and M1 SARAMs
Peripheral Frame 0
0-wait (reads)
Peripheral Frame 3
0-wait (writes)
1-wait (reads)
Assumes no conflicts between CPU and DMA.
Peripheral Frame 1
Cycles can be extended by peripheral generated ready.
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
Fixed. Cycles cannot be extended by the peripheral.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
0-wait data and
program
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
L5 SARAM
L6 SARAM
L7 SARAM
XINTF
Assumes no CPU conflicts
0-wait data (read)
0-wait data (write)
1-wait program (read)
1-wait program (write)
Programmable
0-wait data (write)
0-wait data (read)
Assumes no conflicts between CPU and DMA.
Programmed via the XTIMING registers or extendable via
external XREADY signal.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum for writes assumes write buffer enabled and
not full.
Assumes no conflicts between CPU and DMA. When DMA
and CPU attempt simultaneous conflict, 1-cycle delay is
added for arbitration.
Programmed via the Flash registers.
1-wait is minimum number of wait states allowed. 1-wait-state
operation is possible at a reduced CPU frequency.
Programmed via the Flash registers.
0-wait minimum for paged access is not allowed
1-wait-state operation is possible at a reduced CPU
frequency.
Wait states of password locations are fixed.
1-wait minimum
0-wait minimum writes
with write buffer
enabled
0-wait data (write)
0-wait data (read)
OTP
Programmable
1-wait minimum
FLASH
Programmable
1-wait Paged min
1-wait Random min
Random
Paged
FLASH Password
16-wait fixed
1-wait
Boot-ROM
0-wait speed is not possible.
(1)
The DMA has a base of 4 cycles/word.
The F2833x (C28x+FPU) family is a member of the TMS320C2000 digital signal controller (DSC)
platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing
C28x DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point-unit (FPU). It is a very
efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The device is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the F2833x and its 64-bit processing capabilities, enable it to efficiently handle higher
numerical resolution problems. Add to this the fast interrupt response with automatic context save of
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Functional Overview
39
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