參數(shù)資料
型號(hào)： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號(hào)控制器（DSC）
文件頁數(shù)： 134/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
(A)
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 0) (continued)
NO.
19
MIN
35
35
MAX
UNIT
ns
ns
ns
t
su(SIMO-SPCL)S
t
su(SIMO-SPCH)S
t
v(SPCL-SIMO)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity
= 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity
= 1)
20
0.5t
c(SPC)S-10
t
v(SPCH-SIMO)S
0.5t
c(SPC)S-10
ns
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-36. SPI Slave Mode External Timing (Clock Phase = 1)
(1)(2)(3)(4)
NO.
12
13
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
su(SOMI-SPCH)S
t
su(SOMI-SPCL)S
t
v(SPCH-SOMI)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
Valid time, SPISOMI data valid after SPICLK low (clock polarity =
0)
8t
c(LCO)
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.125t
c(SPC)S
0.125t
c(SPC)S
0.75t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
14
17
18
(1)
(2)
(3)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
(4)
Electrical Specifications
134
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