參數(shù)資料
型號: TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號控制器(DSC)
文件頁數(shù): 41/166頁
文件大?。?/td> 1889K
代理商: TMS320F28335_1
www.ti.com
A
3.2.7
M0, M1 SARAMs
3.2.8
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
3.2.9
Boot ROM
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
devices also contain a single 1K
×
16 of OTP memory at address range 0x380400 – 0x3807FF. The user
can individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that
erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve
higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used
to execute code or store data information. Note that addresses 0x33FFF0 – 0x33FFF5 are reserved for
data variables and should not contain program code.
NOTE
The F28335/F28334/F28332 Flash and OTP wait-states can be configured by the
application. This allows applications running at slower frequencies to configure the flash to
use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the
TMS320F2833x Digital Signal Controller (DSC) System Control and Interrupts
Reference Guide
(literature number
SPRUFB0
).
All F2833x devices contain these two blocks of single access memory, each 1K
×
16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to
execute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.
The F28335 and F28334 each contain an additional 32K
×
16 of single-access RAM, divided into 8 blocks
(L0-L7 with 4K each). The F28332 contains an additional 24K
×
16 of single-access RAM, divided into
6 blocks (L0-L5 with 4K each). Each block can be independently accessed to minimize CPU pipeline
stalls. Each block is mapped to both program and data space. L4, L5, L6, and L7 are DMA accessible
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
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Functional Overview
41
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