
DMA Registers
11-14
Table 11–5.START (AUX START) Field Descriptions
START (AUX START)
Bit Nos:
23 – 22
(25 – 24)
Description
0 0
DMA channel reset. DMA-channel read or write cycles in progress are completed
(not aborted); any data read is ignored. Any pending (not started) read or write is
canceled. The auxiliary (AUX START =00
2
) and primary (START=00
2
) transfer
counters are set to zero. The DMA channel is reset so that when it starts, a new
transaction begins; that is, a read is performed. In this mode, stopping is immediate
with no other registers loaded.
0 1
DMA halt on read or write boundary. Halts the DMA channel on the first available
read or write boundary. If a read or write has begun, the read or write is completed
before stopping. If a read or write has not begun, no read or write is started. In this
mode, stopping is immediate with no other registers loaded).
1 0
DMA halt on transfer boundary. Halts the DMA channel on the first available transfer
boundary. If a DMA transfer has begun, the entire transfer is completed, including
both cycles (both read and write operations), before stopping. If a transfer has not
begun, none is started. In this mode, stopping is immediate with no other registers
loaded. This is also the value after a DMA transfer completes.
1 1
DMA start. Writing 11
2
to this field starts the DMA process using the values in the
channel’s DMA channel registers (Figure 11–1). If the DMA is in autoinitialization, all
DMA registers are loaded before starting the operation. The DMA coprocessor starts
from reset if previously reset (START or AUX START bits = 00
2
) or restarts from the
previous state if previously halted (START or AUX START bits = 01
2
or 10
2
).
Table 11–6.STATUS (AUX STATUS) Field Descriptions
STATUS (AUX
STATUS)
Bit Nos:
27 – 26
(29 – 28)
Description
0 0
The DMA channel is held on the boundary of the DMA transfer (the write is com-
plete, and the read has not begun). This is the value at RESET after a halt on a
transfer boundary or after a block transfer.
0 1
The DMA channel is being held in the middle of a DMA transfer; (the read is com-
plete, and the write has not begun). This occurs only if the START (or AUX START)
field = 01
2
.
1 0
Reserved.
1 1
The DMA channel is not being held or reset.