
Bootloading from External Memory (Examples)
10-10
10.4 Bootloading from External Memory (Examples)
When the ’C4x’s ROMEN input pin is high and RESETLOC(1,0)=00
2
during
reset, the memory bootloader can load programs stored in off-chip memory
(typically 8-, 16-, or 32-bit ROMs) at an address determined by the IIOF pins
to any valid external or internal memory in the ’C4x’s memory map.
Because address zero (0) is reserved for the bootloader, address
zero should not be used for the
reset vector when a user-defined,
internal ROM-code mask is used.
The 8 LSBs of the first word of data read stream specify the memory width (8,
16, or 32 bits) as shown in Table 10–3, Table 10–4, and Table 10–5.
8-bit memories:
16-bit memories:
32-bit memories:
08h
0010h
0000 0020h
If 8- or 16-bit external memories are used, the loading sequence is from LSBs
to MSBs. The bootloader reads the contents of 16-bit wide memories (least
significant half word first) and packs each pair of 16-bit half words to make a
32-bit word before loading each word to memory. Accordingly, the bootloader
reads the contents of byte-wide memories (least significant byte first) and
packs each group of four bytes into a 32-bit word before loading each word to
memory. Because the bootloader packs bytes before loading, no external
hardware is needed to pack the loaded bytes into a 32-bit word. For 32-bit wide
external memories, no byte packing is necessary, because the memory data
width matches that of the ’C4x.
For 16-bit memories, the data read is expected to be in bit positions 0–15.
Thus, the half-word memory’s data lines should be interfaced to ’C4x data lines
(L)D15–0. For byte-wide memories, the data read is expected to be in bit posi-
tions 0–7. Hence, the byte-wide memory’s data lines should be interfaced to
’C4x data lines (L)D7–0. Even though the ’C4x does not require that unused
data lines be pulled up to V
CC
, it is recommended that each unused data line
be pulled up through separate 22 K
resistors to 5 volts for minimum power
dissipation.
Table 10–3, Table 10–4, and Table 10–5 show example data streams for 8-bit,
16-bit, and 32-bit wide configured memories, respectively.