
Programmable Wait States
9-14
9.4
Programmable Wait States
The ’C4x has its own internal software-configurable ready-generation capabil-
ity for each strobe. This software wait-state generator is controlled by configur-
ing two fields in the global or local interface control register. Use the STRBx
WTCNT field (bits 8–10 and 11–13) to specify the number of software wait
states to generate, and use the STRBx SWW field (bits 6–7, and 4–5) to select
one of the following four modes of wait-state generation:
External RDY (SWW = 0). Wait states are generated solely by the external
RDY line (software wait-states ignored).
WTCNT-generated RDY
wtcnt
 (SWW = 01
2
). Wait states are generated
solely by the software wait-state generator (external RDY ignored).
Logical-OR of RDY and RDY
wtcnt
 (SWW = 10
2
). Wait states are generated
with a logical OR of internal and external ready signals. Either signal can
generate ready.
Logical-AND of RDY and RDY
wtcnt
 (SWW = 11
2
). Wait states are gener-
ated with a logical AND of internal and external ready signals. Both signals
must occur.
The four modes are used to generate the internal ready signal, RDY
int
, that
controls accesses. As long as RDY
int 
= 1, the current external access is ex-
tended. When  RDY
int 
= 0, the current access completes. Since the use of
programmable wait states for both external interfaces is identical, only the
global-bus interface is described in this section.
RDY
wtcnt
 is an internally-generated ready signal. When an external access is
begun, the value in WTCNT is loaded into a counter. WTCNT can be any value
from 0 through 7. The counter is decremented every H1/H3 clock cycle until
it becomes 0. Once the counter is cleared to 0, it remains cleared to 0 until the
next access. When the counter is nonzero, RDY
wtcnt
=1. When the counter is
0, RDY
wtcnt
=0.
Table 9–6 is the truth table for each value of SWW, showing the different val-
ues at RDY, RDY
wtcnt, 
and
RDY
int
.
Note:
At reset, the ’C4x inserts seven wait states for each access to external
memory. These wait states are inserted to ensure that the system can func-
tion with slow memories. To increase system performance when using fast
external memories, you will need to decrease the number of wait states.