參數(shù)資料
型號(hào): TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
文件頁(yè)數(shù): 52/59頁(yè)
文件大?。?/td> 306K
代理商: TLC320AD52C
6–2
6.1
Control 1 Register
Table 6–2. Control 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
Software reset
0
Software reset not asserted
1
Software power down (analog and filters)
0
Software power down (not asserted)
1
Select AUXP and AUXM for ADC
0
Select INP and INM for ADC
0
Select INP and INM for monitor
1
Select AUXP and AUXM for monitor
1
1
Monitor amplifier gain = –18 dB (see Note 1)
1
0
Monitor amplifier gain = –8 dB (see Note 1)
0
1
Monitor amplifier gain = 0 dB (see Note 1)
0
0
Monitor amp mute
1
Digital loopback asserted
0
Digital loopback not asserted
1
16-bit DAC mode (hardware secondary requests)
0
Not 16-bit DAC mode (software secondary requests)
Default value: 0 0 0 0 0 0 0 0
NOTE 1: These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
A software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write
a 0 to end the master reset operation. Writing 0s to the reserved bits is suggested.
6.2
Control 2 Register
Table 6–3. Control 2 Register
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
X
FLAG output value
1
Phone mode enable
0
Phone mode disable
X
Decimator FIR overflow flag (valid only during read cycle)
1
16-bit ADC mode
0
Not-16-bit ADC mode
X
0
0
Reserved (TLC320AD50C only)
0
0
0
FSD enable (TLC320AD52C only)
1
FSD disable (TLC320AD52C only)
1
Analog loopback enabled
0
Analog loopback disabled
Default value: 00000000
Writing 0s to the reserved bits is suggested.
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