參數(shù)資料
型號: TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號轉(zhuǎn)換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號轉(zhuǎn)換)
文件頁數(shù): 5/59頁
文件大?。?/td> 306K
代理商: TLC320AD52C
v
List of Illustrations
Figure
Title
Page
2–1 Timing Sequence of ADC Channel (Primary Communication Only)
2–2 Timing Sequence of ADC Channel (Primary and Secondary Communication)
2–3 Timing Sequence of DAC Channel (Primary Communication Only)
2–4 Timing Sequence of DAC Channel (Primary and Secondary Communication)
2–5 Register 1 Read Operation Timing Diagram
2–6 Register 1 Write Operation Timing Diagram
2–7 Internal Power-Down Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves)
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2–9 Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Master Device FS and FSD Output When FSD Register
(D0–D5, Control Register 3) is 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 Master Device FS and FSD Output After Control Register 3 Is Programmed
(One Slave Device)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Master With Slaves (To DSP Interface)
2–13 Master-Slave Frame-Sync Timing After A Delay Has Been Programmed
Into The FSD Register (D0–D5 of Control Register 3)
2–14 Master Device FS and FSD Output After
Control Register 3 Is Programmed with 49H
2–15 RC Antialias Filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–16 INP and INM Internal Self-Biased (2.5 V) Circuit
2–17 Differential Output Drive (Ground Referenced)
3–1 Primary Serial Communication Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Hardware and Software Methods to Make a Secondary Request
3–3 FS Output When Hardware Secondary Serial Communication
Is Requested Only Once (No Slave)
3–4 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (Three Slaves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 FS Output During Software Secondary Serial Communication Request (No Slave)
3–6 Phone Mode Timing When Phone Mode is Enabled
3–7 Primary Communication DIN and DOUT Data Format
3–8 Secondary Communication DIN and DOUT Data Format
4–1 ADC Decimation Filter Response
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 ADC Decimation Filter Passband Ripple
4–3 DAC Interpolation Filter Response
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 DAC Interpolation Filter Passband Ripple
2–2
2–2
2–3
2–3
2–4
2–5
2–7
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2–9
2–9
2–10
2–11
2–12
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2–12
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2–13
2–14
2–14
2–15
3–1
3–2
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3–3
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3–3
3–4
3–4
3–5
3–5
4–7
4–7
4–8
4–8
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