參數(shù)資料
型號(hào): TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
文件頁(yè)數(shù): 22/59頁(yè)
文件大?。?/td> 306K
代理商: TLC320AD52C
2–8
2.3
MCLK is the external master clock input. The internal clock circuit generates and distributes necessary
clocks throughout the device. An internal PLL circuit is used for upsampling to provide the appropriate clocks
for the digital filters and modulators.
Master Clock Circuit
When the device is in the master mode, SCLK and FS are derived from MCLK in order to provide clocking
of the serial communications between the device and a DSP (digital signal processor). When in the slave
mode, SCLK and FS are both inputs.
2.4
DOUT is placed in the high-impedance state on the rising edge of the frame sync. In the primary
communication, the data word is the ADC conversion result. In the secondary communication, the data is
the register-read results when requested by the read/write (R/W) bit. If a register read is not requested, the
low eight bits of the secondary word are all zeroes. The state of the master/slave (M/S) terminal is reflected
by the MSB in secondary communication (DOUT, bit DS15) and the LSB in the primary communication
(DOUT, bit D0). When the device is in the slave mode, DOUT remains in a high-impedance state until a
nonzero value is written as a number of slaves in control register 3 (bits D7 and D6).
Data Out (DOUT)
2.4.1
In the master mode, DOUT is taken from the high-impedance state by the falling edge of the master frame
sync (FS). The most significant data bit then appears first on DOUT.
Data Out, Master Mode
2.4.2
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the frame sync (FS).
The most significant data bit then appears on DOUT. When in the slave mode, DOUT is not enabled until
the control 3 register is programmed with the number of slaves. This must be done even if there is only one
slave device.
Data Out, Slave Mode
2.5
In a primary communication, the data word is the input digital signal to the DAC channel. If the (15+1)-bit
data format is used, the LSB (D0) is used to request a secondary communication. In a secondary
communication, the data is the control and configuration data that sets the device for a particular function
(see Section 3, Secondary Serial Communication for details).
Data In (DIN)
2.6
The FC input provides for hardware requests for secondary communications. FC works in conjunction with
the LSB of the primary data word. The signal on FC is latched on the rising edge of the primary frame sync
(FS). FC should be tied low if not used.
FC (Hardware Secondary Communication Request)
2.7
The frame-sync signal (FS) indicates the device is ready to send and receive data. The data transfer out
of DOUT and into DIN begins on the falling edge of the frame-sync signal.
Frame-Sync Function for TLC320AD50C
相關(guān)PDF資料
PDF描述
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