參數(shù)資料
型號(hào)： TLC320AD52C
廠(chǎng)商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述： sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號(hào)轉(zhuǎn)換）
文件頁(yè)數(shù)： 21/59頁(yè)
文件大?。?/td> 306K
代理商： TLC320AD52C
2–7
2.2
2.2.1
Reset and Power-Down Functions
Software and Hardware Reset
The TLC320AD50C and TLC320AD52C reset the internal counters and registers in response to either of
two events:
1.
A low-going reset pulse is applied to terminal RESET
2.
A 1 is written to the programmable software reset bit (D7 of control register 1)
Either event resets the control registers and clears all the sequential circuits in the device. Reset signals
should be at least 6 master clock periods long.
2.2.2
Software and Hardware Power Down
Except for the digital interface, most of the device enters the power-down mode when D6 in control register
1 is set to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register
contents are preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize
pops and clicks.
The amount of power drawn during software power down is higher than it is during a hardware power down
because of the current required to keep the digital interface active. Additional differences between software
and hardware power-down modes are detailed in the following paragraphs. Figure 2–7 represents the
internal power-down logic.
PWRDWN
D6 is Programmed
Through a Secondary
Write Operation
Software Power Down
(Control Register 1, D6)
Internal TLC320AD50C
Figure 2–7. Internal Power-Down Logic
2.2.2.1
Software Power Down
When D6 of control register 1 is set to 1, the device enters the software power-down mode. In this state,
the digital interface circuit is still active while the internal ADC and DAC channels and differential outputs
OUTP and OUTM are disabled, and DOUT and FSD are inactive. Register data in the secondary serial
communications is still accepted, but data in the primary serial communications is ignored. The device
returns to normal operation when D6 of control register 1 is reset to 0.
2.2.2.2
Hardware Power Down
When PWRDWN is held low, the device enters the hardware power-down mode. In this state, the internal
clock control circuit and the differential outputs OUTP and OUTM are disabled. All other digital I/Os either
are disabled or remain in the state they were in immediately before power down. DIN cannot accept any data
input. The device can only be returned to normal operation by taking and holding PWRDWN high. When
not holding the device in the hardware power-down mode, PWRDWN should be tied high.
相關(guān)PDF資料
PDF描述
TLC320AD55C Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56C Sigma-Delta Analog Interface Circuit
tlc320ad56c Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
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TLC320AD535C-I 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
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