參數(shù)資料
型號(hào): TLC320AD52C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述: sigma - delta模擬接口電路的主從功能(帶主從功能的Σ△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
文件頁(yè)數(shù): 26/59頁(yè)
文件大?。?/td> 306K
代理商: TLC320AD52C
2–12
2.7.4
The master FSD is output to the first slave and the first slave FSD is output to the second slave device and
so on (see figure 2–12). The FSD output of each device is input to the FS terminal of the succeeding device.
The FSD timing sequence in the slave mode is as follows:
Frame-Sync Delayed (FSD), Slave Mode
When the FSD register data is 0, then FSD goes low 1/4 SCLK cycle before FS goes low.
When the FSD register data is greater than 17, then FSD goes low on the rising edge of the SCLK
that is equal to the FSD register number of SCLKs after the falling edge of FS (see figure 2–13).
Data values from 1 to 17 should not be used.
CLKOUT
DR
DX
CLKOUT
DOUT
DIN
FSD
CLKX
CLKR
SCLK
FSX
FSR
FS
SCLK
DOUT
FS
SCLK
DOUT
FS
DIN
MCLK
FSD
DIN
MCLK
FSD
Master
TMS320C5X
TMS320C2X
TMS320C54X
Slave 1
Slave 2
SCLK
DOUT
FS
DIN
MCLK
Slave 3
Figure 2–12. Master With Slaves (To DSP Interface)
P
P
P
P
S
128 SCLKs
S
Master FS
Master FSD
Slave 1 FS
S
Delay 1
Delay 2
Delay 3
Delay 4
Slave 1 FSD
Slave 2 FS
Slave 2 FSD
Slave 3 FS
Slave 3 FSD
(see note)
M
S1
S2
S3
M
S1
NOTE: Slave 3 FSD cannot be used.
Figure 2–13. Master–Slave Frame-Sync Timing After A Delay Has Been Programmed Into The
FSD Register (D0–D5 of Control Register 3)
相關(guān)PDF資料
PDF描述
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