參數(shù)資料
型號(hào)： TLC320AD52C
廠商： Texas Instruments, Inc.
英文描述： Sigma-Delta Analog Interface Circuits With Master-Slave Function(帶主從功能的∑△模擬接口電路,高分辨率信號(hào)轉(zhuǎn)換)
中文描述： sigma - delta模擬接口電路的主從功能（帶主從功能的Σ△模擬接口電路，高分辨率信號(hào)轉(zhuǎn)換）
文件頁(yè)數(shù)： 20/59頁(yè)
文件大?。?/td> 306K
代理商： TLC320AD52C
2–6
2.1.6
The sigma–delta analog-to-digital converter in the device is a sigma–delta modulator with 64-
×
oversampling. The ADC provides high-resolution, low-noise performance using oversampling techniques.
Due to the oversampling employed, only single-pole antialiasing filters are required on the analog inputs.
Sigma–Delta ADC
2.1.7
The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of the decimation filter is a 16-bit 2’s-complement data word clocking at the
sample rate selected for that particular data channel. The bandwidth of the filter is 0.439
×
f
sample
and scales
linearly with the sample rate.
Decimation Filter
2.1.8
The sigma–delta digital-to-analog converter in the device is a sigma–delta modulator with 256-
×
oversampling. The DAC provides high-resolution, low-noise performance using oversampling techniques.
Sigma–Delta DAC
2.1.9
The interpolation filter resamples the digital data at a rate of 256 times the incoming sample rate. The
high-speed data output from the interpolation filter is then used in the sigma–delta DAC. The bandwidth of
the filter is 0.439
×
f
sample
and scales linearly with the sample rate.
2.1.10
Analog and Digital Loopback
The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can
be used for in-circuit system-level tests. The analog loopback routes the DAC low-pass filter output into the
analog input where it is then converted by the ADC into a digital word. The digital loopback, enabled by
setting bit D1 in control 1 register to 1, routes the ADC output to the DAC input on the device. Analog
loopback is enabled by setting bit D3 in control 2 register to 1 (see section 6).
Interpolation Filter
2.1.11
The decimator FIR filter sets an overflow flag (bit D5) of control 2 register to indicate that the input analog
signal has exceeded the range of the internal decimation filter calculations. Once the FIR overflow flag has
been set in the register, it remains set until the register is read by the user. Reading this value resets the
overflow flag.
FIR Overflow Flag
If FIR overflow occurs, the input signal must be attenuated either by the PGA or some other method.
相關(guān)PDF資料
PDF描述
TLC320AD55C Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
TLC320AD56C Sigma-Delta Analog Interface Circuit
tlc320ad56c Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路)
TLC320AD57(中文) Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD52CDW 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
TLC320AD52CPT 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱(chēng):296-21257-2
TLC320AD535 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
TLC320AD535C 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
TLC320AD535C-I 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*