參數(shù)資料
型號(hào)： TCM4400ETQFP
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語(yǔ)音的A / D和D / A射頻接口電路
文件頁(yè)數(shù)： 58/64頁(yè)
文件大?。?/td> 888K
代理商： TCM4400ETQFP
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
58
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
auxiliary functions control register 2 (see Table 33)
The values in the auxiliary function control register No. 2 set the operation parameters as described below:
APCSPD:
When cleared to 0, the APC clock is at 4 MHz; when set to 1, the APC clock is at 2 MHz.
IAPCPTR:
Setting to 1 initializes the pointer of the APC RAM to the base address. This is not a toggle
bit and has to be set to 0 to set APC RAM operational.
APCMODE:
Select the equation used for APC waveform generation.
AGCW:
If cleared to 0, the automatic gain control path is powered down with the control of GSM
receive window (BDLON terminal) and AGCPD bit. If the AGCPD bit is set to 1, the
power down is controlled by AGCPD bit.
AGCPD:
This bit is functionally associated with AGCW bit. When this bit is set to 1, the automatic
gain control path is in power-down mode.
APCW:
If 0, the RF power control path is down powered with the control of GSM transmit window
(BULON) and with the control of APCPD bit. If the APCPD bit is set to 1, power down is only
controlled by APCPD bit.
APCPD:
This bit is functionally associated with the BBULW bit. When this bit is set to 1, the RF power
control path is in power-down mode.
Table 33. AUX Functions Control Register No. 2
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auxiliary A/D converter output register
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AGCW
AGCPD
APCW
APCPD
ááá
áááááá
IAPCTR
APCMODE
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ááááááááá
0
APCSPD
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1
0
1
0
0
1/0
0
0
0
0
0
0
0
0
0
<–VALUE AT RESET
This register is read-only; however, if there is an attempt to write into it, an A/D conversion operation starts; see
Table 34. When the A/D conversion is finished, the AUXADC register is loaded and the A/D converter is
automatically down powered. During the conversion process the ADCEOC bit of the BSTATUS register is set.
This bit is reset automatically after AUXADC is loaded.
Table 34. AUX A/D Converter Output Register
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BIT 9 to 0:
Output pf the 10-bit monitoring ADC.
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R/W
0
0
R/W
R/W
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
<–VALUE AT RESET
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