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| 型號： | TCM4400ETQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 54/64頁 |
| 文件大?。?/td> | 888K |
| 代理商： | TCM4400ETQFP |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
54
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
voiceband control register
The values in the voiceband control register have the meaning shown in Table 22.
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VALOOP:
When set to 1, the internal analog loop of output samples are sent to the audio input
terminal; standard audio paths are connected together, and auxiliary audio paths are
connected together.
VBCTL3: VOICEBAND CONTROL REGISTER
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ADDRESS: 12
R/W
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VIZBUS:
When set to 1, VFS, VCLK, and VDX are put in a hi-Z state when there is nothing to transfer
to the DSP. When cleared to 0, VFS and VCLK are put in V
SS
when there is nothing to
transfer to the DSP, and the VDX bus drives an undefined value (value depends on the
previous serial data transfers).
VRST:
When 1, resets the digital parts of the audio codec (digital filter and modulator). This is not a
toggle bit and has to be set to 0 to remove the reset condition
DAION:
When cleared to 0, the DAI block is in power down; when set to 1, the DAI block is active.
VDAI:
Writing a 1 to this bit starts the SSCLK (104 kHz DAI clock) on reception of the first sample.
This bit is automatically reset to 0 by SSRST after reception of the last sample.
RESERVD:
Reserved bits for testing
DAIMD (0–1):
DAI mode selection as given in Table 23.
VCLKMODE:
When cleared to 0, allows selection of VCLK in burst mode. When set to 1, allows selection
of VCLK in continuous mode.
Table 23. DAI Mode Selection
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1
1
Test of acoustic devices and A/D and D/A (voice path)
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