
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
57
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
automatic frequency control registers (1 and 2)
The content of the APC RAM describes the shape of the ramp-up and ramp-down control; see Table 30.
Table 30. APC Ramp Control
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Actual shape values (five bits long) are contained in the shape D/A converter input register as shown in
Table 31.
APCRAM: AUTOMATIC POWER CONTROL RAM
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ADDRESS: 17 (64 Words)
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W
<—VALUE AT RESET
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RDWNWORD62 (5BIT)
RUP WORD62 (5 BIT)
1
0
0
0
1
0
RDWNWORD63 (5BIT)
X
X
X
RUP WORD63 (5 BIT)
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1
0
0
<—ACCESS TYPE
0
1
0
W
W
W
X
W
W
W
W
W
W
X
W
X
X
X
X
X
Table 31. Shape DAC Input Register
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BIT 4–0:
Input of the 5-bit APC DAC.
RESERVD
R = 0
RESERVD
RESERVD
R = 0
RESERVD
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RESERVD
BIT4
BIT3
BIT2
BIT1
R/W
BIT0
R/W
1
0
<–ACCESS TYPE
0
1
0
1/0
0
0
R = 0
R = 0
R = 0
R/W
R/W
0
0
R/W
0
0
0
0
0
0
<–VALUE AT RESET
RESERVD:
Reserved bits for testing
AGC control register
The AGC control register is 10-bits wide and controls operations of the analog AGC circuit as shown in Table 32.
Table 32. Analog AGC Gain Control Register
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BIT 9 to 0:
Input of the 10-bit AAGC DAC.
AUXAGC: AUTOMATIC GAIN CONTROL REGISTER
ADDRESS: 19
R/W
R/W
BIT9
BIT8
BIT7
BIT6
R/W
BIT5
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BIT4
BIT3
BIT2
BIT1
R/W
BIT0
1
<–ACCESS TYPE
0
0
1
1
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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RESERVD:
Reserved bits testing.