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參數(shù)資料
| 型號： | TCM4400ETQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 24/64頁 |
| 文件大小： | 888K |
| 代理商： | TCM4400ETQFP |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
voiceband serial interface timing considerations
Figure 5 shows the timing diagram for both transmit and receive voiceband serial interface operation.
The signal VCLK is the output serial clock used to control the transmission or reception of the data (see
Figure 5). The transmitted serial data (VDX) is the serial data output; the frame synchronization (VFS) is used
to initiate the transfer of transmit and receive data. The received data (VDR) is the serial data input.
Each serial port includes four registers that include the data transmit register (DXR), the data receive register
(DRR), the transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface; one extra cycle is
generated before VFS, and two extra cycles are generated after the LSB.
XLOAD and RLOAD are internal signals.
VCLK
tsu7
th6
tsu8
th8
VFS
VDX
XLOAD
A15
A14
A13
A12
A3
A2
A1
A0
MSB
LSB
DXR
Loaded
XSR
Loaded
a. Audio-Serial-Port Transmit Operation
VCLK
tsu9
th7
VFS
VDR
RLOAD
A15
A14
A13
A12
A3
A2
A1
A0
MSB
LSB
DDR
Loaded
b. Audio-Serial-Port Receive Operation
Figure 5. Voiceband Serial Interface Timing Waveforms
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