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參數(shù)資料
| 型號： | TCM4400ETQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 36/64頁 |
| 文件大?。?/td> | 888K |
| 代理商： | TCM4400ETQFP |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
JTAG interface
TCM4400E provides a JTAG interface according to IEEE Std1149.1. This interface uses five dedicated IOs:
TCK (test clock), TMS (test mode select), TDI (scan input), TDO (scan output), and TRST (test reset). Inputs
TMS,TDI, and TRST contain a pullup device which makes their state high when they are not driven. Output TDO
is a 3-state output which is Hi-Z except when data are shifted between TDI and TDO. TRST input is intended
for proper initialization of the state machine test access port (TAP) and boundary scan cells. System RESET
is sent into the device through a boundary-scan register, which has to be initialized by TRST to allow the RESET
signal to be propagated into the device; a good practice should be to connect RESET and TRST terminals
together.
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IDCODE
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connections testing between devices.
of the digital I/Os of the device.
Connects the boundary scan register between TDI and TDO. This mode captures the state of the input
terminals and forces the state of the output pins. This mode is intended for printed-circuit board
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EXTEST
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Connects the identification register between TDI and TDO. This is the default configuration at reset.
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INTEST
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00011
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Connects the boundary scan register between TDI and TDO. This mode forces the internal system input
signals via the parallel latches of the boundary register and captures internal system outputs. The mode
performs device internal tests independently of the state of its input terminals. In this mode the internal
system master clock is derived from TCK and is active in the run-test-idle state of the state machine to
JTAG interface scan chains description
bypass register
1
TDI
0
TDO
instruction register
5
TDI
0
TDO
4
0
3
0
2
0
1
0
identification register
32
TDI
0
TDO
31
0
30
1
29
0
28
0
0
0
0
0
0
0
0
0
0
1
1
27
26
25
24
23
22
21
20
19
18
17
16
0
15
1
14
0
13
1
12
0
0
0
0
0
0
1
0
1
1
1
1
11
10
9
8
7
6
5
4
3
2
1
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